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公开(公告)号：US11482952B1
公开(公告)日：2022-10-25
申请号：US17496747
申请日：2021-10-07
Inventor： Shih-Chieh Wang , Yong-Yi Jhuang , Ming-Fu Tsai
Abstract: A method for determining zero crossing occurrence in an alternating current (AC) signal with constant frequency of a permanent magnet synchronous motor (PMSM) includes: sampling the AC signal to obtain a plurality of data points; starting to count a number of consecutive data points that have sampled values with a same sign in a detection range, to generate a count value, wherein the consecutive data points are included in the plurality of data points; determining whether the count value is equal to a zero crossing determination value; and in response to the count value being equal to the zero crossing determination value, determining that a zero crossing occurs at a last data point of the consecutive data points.
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42.发明申请公开(公告)号：US20220223213A1
公开(公告)日：2022-07-14
申请号：US17149689
申请日：2021-01-14
Inventor： MING-XUN WANG , CHIH-HAO CHEN , JI-JR LUO
Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.
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公开(公告)号：US20240405719A1
公开(公告)日：2024-12-05
申请号：US18326034
申请日：2023-05-31
Inventor： YAO-WEI YANG
IPC: H03B5/12 , H03B5/04 , H03K3/0231
Abstract: A voltage mode controlled liner frequency modulation oscillator comprises a voltage modulation circuit, a reference current generating circuit, and an oscillating circuit. The voltage modulation circuit is configured to generate a modulation voltage according to a feedback voltage and a first reference voltage. The reference current generating circuit, coupled to the voltage modulation circuit, is configured to generate a first reference current according to the modulation voltage and a second reference voltage. The oscillating circuit, coupled to the reference current generating circuit, is configured to generate an oscillating signal with an oscillating frequency according to the first reference current, wherein the oscillating frequency varies with the modulation voltage.
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公开(公告)号：US20240322798A1
公开(公告)日：2024-09-26
申请号：US18125331
申请日：2023-03-23
Inventor： Chih-Sheng CHANG , Isaac Y. CHEN
CPC classification number: H03K3/017 , H03K3/037 , H03K19/20 , H04R3/00 , H04R29/001
Abstract: An electronic device includes a sampling circuit and a summing circuit coupled with the sampling circuit. The sampling circuit samples a pulse width of a first input pulse of a PWM input signal since a first time point on a rising edge of a clock pulse of a clock signal. The summing circuit generates a first output pulse of a PWM output signal since a second time point on a falling edge of the clock pulse. A pulse width of the first output pulse is a summation of the pulse width of the first input pulse and a pulse width of a second input pulse of the PWM input signal, and the second input pulse is the next pulse after the first input pulse.
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公开(公告)号：US12040693B2
公开(公告)日：2024-07-16
申请号：US17872024
申请日：2022-07-25
Inventor： Yao-Wei Yang
CPC classification number: H02M1/0009 , H02M3/156
Abstract: A control circuit for controlling a DC-DC converter is provided. The control circuit comprises a first sensor, second sensor, error amplifier, signal conditioning circuit, first comparison circuit, second comparison circuit, and driver circuit. The error amplifier is configured to receive a feedback voltage and a reference voltage for generating a first voltage. The signal conditioning circuit is configured to receive the first voltage for generating a second voltage and a third voltage. The first comparison circuit is configured to make a comparison based on a first sensing signal from the first sensor and the second voltage for generating a first comparison signal. The second comparison circuit is configured to make a comparison based on a second sensing signal from the second sensor and the third voltage for generating a second comparison signal. The driver circuit is for driving a power stage according to the first and second comparison signals.
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Patent Agency Ranking
公开(公告)号：US20240063717A1
公开(公告)日：2024-02-22
申请号：US17892154
申请日：2022-08-22
Inventor： YAO-REN CHANG
IPC: H02M3/158
CPC classification number: H02M3/158
Abstract: A control circuit for adaptive noise margin control for a constant on time (COT) converter comprises an input reference terminal, amplifier, first switch device, voltage divider, trigger circuit, and output reference terminal. The amplifier has an input terminal coupled to the input reference terminal receiving a reference voltage signal. The first switch device has a control terminal coupled to an output of the amplifier, a first conduction terminal for receiving a voltage source signal, and a second conduction terminal. The voltage divider is coupled to the second conduction terminal and another input terminal of the amplifier. The trigger circuit, coupled to the voltage divider, is for triggering voltage change of a modified reference voltage signal selectively according to a high-side control signal of the COT converter. The output reference terminal coupled to the second conduction terminal outputs the modified reference voltage signal.
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公开(公告)号：US20240022857A1
公开(公告)日：2024-01-18
申请号：US17864182
申请日：2022-07-13
Inventor： Hsin-Yuan CHIU , Chia-Ling Hsieh
Abstract: A device for audio signal processing includes a main processor and two audio processors electrically connected with the main processor. Each audio processor corresponds to a channel of a stereo audio output. The main processor provides an indication signal for the two audio processors. Each audio processor generates a synchronization signal according to the indication signal and performs audio signal processing according to the synchronization signal. The synchronization signals begin simultaneously and have the same frequencies that equal a sampling frequency. Each synchronization signal includes at least one pulse, and a start of each pulse of each synchronization signal is aligned in time with a start of a pulse of the indication signal. The audio signal processing performed by each audio processor begins at an end of one of the at least one pulse in the synchronization signal corresponding to the audio processor.
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公开(公告)号：US11764678B2
公开(公告)日：2023-09-19
申请号：US17580663
申请日：2022-01-21
Inventor： Yao-Ren Chang
CPC classification number: H02M3/1582 , H02M1/0096 , H02M1/0025
Abstract: A constant on time converter control circuit and a constant on time converter are provided. The constant on time converter control circuit comprises an error amplifier, a voltage to current converter, and an initial current source. The error amplifier is for receiving a reference voltage signal and a feedback voltage signal and outputting a compensated voltage signal. The voltage to current converter receives the compensated voltage signal and outputs a converted current signal. The initial current source provides an initial current signal. The initial current signal and the converted current signal form a new reference voltage signal. A constant on time OFF time comparator receives the new reference voltage signal and the feedback voltage signal and outputs a control signal. The control signal affects the turning on and turning off of electronic switches to produce an output voltage of a constant on time converter.
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公开(公告)号：US11757420B2
公开(公告)日：2023-09-12
申请号：US17324135
申请日：2021-05-19
Inventor： Jung-Kuei Chang
Abstract: A leveling equalizer includes a graphic equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a gain control circuit. The graphic equalizer circuit processes a first input signal and output a first output signal and a second output signal. The first multiplication circuit multiplies the first output signal and one of an adjustable gain value and a fixed gain value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and another of the adjustable gain value and the fixed gain value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The gain control circuit dynamically adjusts the adjustable gain value according to the equalizer output signal.
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公开(公告)号：US11742856B2
公开(公告)日：2023-08-29
申请号：US17535725
申请日：2021-11-26
Inventor： Shu-Han Nien
IPC: H03K19/003 , H03K19/00 , G11C7/10
CPC classification number: H03K19/00384 , H03K19/0027 , G11C7/1057 , G11C7/1084
Abstract: A digital buffer device with self-calibration includes a first buffer circuit, detection circuit, and calibration circuit. The first buffer circuit has a buffer input terminal for receiving an input signal and a buffer output terminal as output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to indicate circuit characteristic variations of the at least one second buffer circuit. The at least one second buffer circuit is of a same type of buffer as the first buffer circuit. The calibration circuit has a calibration input terminal for receiving the input signal, and a calibration output terminal coupled to the buffer output terminal. The calibration circuit is for calibrating the first buffer circuit to generate an output signal according to the input signal and the at least one detection signal.
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