公开(公告)号：US20100329058A1

公开(公告)日：2010-12-30

申请号：US12868341

申请日：2010-08-25

申请人： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

发明人： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

IPC分类号： G11C7/00

CPC分类号： G11C7/1045 ,  G06F12/0877 ,  G06F12/0882 ,  G06F12/0893 ,  G06F2212/1028 ,  G11C7/1027 ,  G11C7/12 ,  G11C11/418 ,  G11C2207/104 ,  G11C2207/2245 ,  Y02D10/13

摘要： A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.

摘要翻译： 处理器包括高速缓冲存储器。 高速缓冲存储器包括单元阵列，字线和位线。 控制模块使得字线的字线能够访问所启用的字线中的第一单元。 控制模块禁用字线并将字线保持在禁用状态，以访问字线中的第二个单元格。

公开(公告)号：US07523271B2

公开(公告)日：2009-04-21

申请号：US11324592

申请日：2006-01-03

申请人： Matthew B. Houzenga ,  Alan G. McClure

发明人： Matthew B. Houzenga ,  Alan G. McClure

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0893 ,  G06F12/0877 ,  G06F12/0888

摘要： An apparatus, system, and method are disclosed for regulating the number of write requests in a fixed-size cache that facilitates differentiated treatment of write requests based on an assigned pacing value. The apparatus includes an examination module to examine a pending write request issued by an application. A priority module determines a priority for the write request based on an operating system defined input/output priority value. An assessment module assesses a storage demand level for storing write requests in a fixed-size cache. An assignment module assigns a pacing value to the write request based on the priority and in response to the storage demand level. A permission module permits the application to issue a subsequent write request once the pacing value of the write request is satisfied. The pacing value is satisfied by waiting until the amount of time specified by the pacing value expires.

摘要翻译： 公开了一种用于调节固定大小的缓存中的写入请求数量的装置，系统和方法，其有助于基于所分配的起搏值来区分对写入请求的处理。 该装置包括检查应用程序发出的未决写入请求的检查模块。 优先级模块基于操作系统定义的输入/输出优先级值确定写入请求的优先级。 评估模块评估在固定大小的缓存中存储写入请求的存储需求级别。 分配模块根据优先级和响应于存储需求级别为写入请求分配起搏值。 一旦满足写入请求的起搏值，许可模块允许应用程序发出后续写入请求。 通过等待直到起搏值指定的时间过期才能满足起搏值。

公开(公告)号：US20070156961A1

公开(公告)日：2007-07-05

申请号：US11324592

申请日：2006-01-03

申请人： Matthew Houzenga ,  Alan McClure

发明人： Matthew Houzenga ,  Alan McClure

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0877 ,  G06F12/0888

摘要： An apparatus, system, and method are disclosed for regulating the number of write requests in a fixed-size cache that facilitates differentiated treatment of write requests based on an assigned pacing value. The apparatus includes an examination module to examine a pending write request issued by an application. A priority module determines a priority for the write request based on an operating system defined input/output priority value. An assessment module assesses a storage demand level for storing write requests in a fixed-size cache. An assignment module assigns a pacing value to the write request based on the priority and in response to the storage demand level. A permission module permits the application to issue a subsequent write request once the pacing value of the write request is satisfied. The pacing value is satisfied by waiting until the amount of time specified by the pacing value expires.

摘要翻译： 公开了一种用于调节固定大小的缓存中的写入请求数量的装置，系统和方法，其有助于基于所分配的起搏值来区分对写入请求的处理。 该装置包括检查应用程序发出的未决写入请求的检查模块。 优先级模块基于操作系统定义的输入/输出优先级值确定写入请求的优先级。 评估模块评估在固定大小的缓存中存储写入请求的存储需求级别。 分配模块根据优先级和响应于存储需求级别为写入请求分配起搏值。 一旦满足写入请求的起搏值，许可模块允许应用程序发出后续写入请求。 通过等待直到起搏值指定的时间过期才能满足起搏值。

公开(公告)号：US20060176308A1

公开(公告)日：2006-08-10

申请号：US11267638

申请日：2005-11-04

申请人： Ashish Karandikar ,  Shirish Gadre ,  Stephen Lew ,  Christopher Cheng

发明人： Ashish Karandikar ,  Shirish Gadre ,  Stephen Lew ,  Christopher Cheng

IPC分类号： G06T1/00

CPC分类号： G06T1/60 ,  G06F3/14 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0877 ,  G06T1/20 ,  G09G5/37 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N19/82 ,  H04N19/85 ,  H04N19/86

摘要： A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

公开(公告)号：US06983346B2

公开(公告)日：2006-01-03

申请号：US10435357

申请日：2003-05-09

申请人： Jonathan Y. Zhang

发明人： Jonathan Y. Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0884 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0859 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02D10/13

摘要： This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache hit address. This information is uses for efficient data accesses and forwarding. Registers store the last miss-address and the last hit-address and corresponding valid flags. These hardware features allow reduced tag-RAM accesses and greatly reduce the latency required to fully re-stock a missed cache line.

摘要翻译： 本发明是采用标签旁路控制器来检测与最后一个高速缓存未命中地址和最后一个高速缓存命中地址相同的高速缓存线的存储器访问的高速缓冲存储器。 此信息用于高效的数据访问和转发。 寄存器存储最后一个未命中地址和最后一个命中地址和相应的有效标志。 这些硬件功能允许减少标签RAM访问，并大大减少完全重新存储错过的高速缓存行所需的延迟。

公开(公告)号：US20040098540A1

公开(公告)日：2004-05-20

申请号：US10610763

申请日：2003-07-02

申请人： RENESAS TECHNOLOGY CORP.

发明人： Teruyuki Itoh ,  Naoto Okumura

IPC分类号： G06F013/00 ,  G06F012/00

CPC分类号： G06F12/0855 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

摘要： A branch/prefetch judgement portion, in receipt of a branch request signal, sets a cache access mode switch signal to an nullHnull level. Thus, a cache memory operates in the 1-cycle access mode consuming a large amount of power. In receipt of a prefetch request signal, the branch/prefetch judgement portion sets the cache access mode switch signal to an nullLnull level. Thus, the cache memory operates in the 2-cycle access mode consuming less power.

摘要翻译： 分支/预取判断部分在接收到分支请求信号时将高速缓存访​​问模式切换信号设置为“H”电平。 因此，高速缓存存储器以1周期访问模式工作，消耗大量的功率。 在接收到预取请求信号时，分支/预取判断部分将高速缓存访​​问模式切换信号设置为“L”电平。 因此，高速缓冲存储器以2周期访问模式工作，消耗较少的功率。

公开(公告)号：US5075846A

公开(公告)日：1991-12-24

申请号：US414335

申请日：1989-09-29

申请人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

发明人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F12/0877 ,  G06F9/3834

摘要： A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.

摘要翻译： 提供了具有基于页面的序列化属性的数据处理器。 一组页面描述符和透明的翻译寄存器将序列化属性编码为高速缓存模式。 数据处理器是一个流水线机器，具有至少两个功能单元，它们彼此独立地工作。 功能单元向访问控制器发出访问存储在外部存储器中的信息的请求。 访问控制器用作仲裁机制，并且根据功能单元的请求的发布顺序来授予功能单元的请求。 当存储器访问在页面描述符中被标记为序列化时，访问控制器推迟序列化访问，直到指令序列中所有待处理的存储器访问完成为止。 所有待处理的请求随后以预定的顺序完成，而与功能单元的请求的发布顺序无关，并且完成所有适当的异常处理。 然后完成推迟的序列化访问。

公开(公告)号：US4884198A

公开(公告)日：1989-11-28

申请号：US944422

申请日：1986-12-18

申请人： Robert B. Garner ,  Anant Agrawal

发明人： Robert B. Garner ,  Anant Agrawal

IPC分类号： G06F12/08

CPC分类号： G06F12/0877

摘要： An improved interface between a processor and an external cache system, having particular application for use in high speed computer systems. A cache memory for storing frequently accessed data is coupled to a cache address register (CAR). A processor generates addresses which correspond to locations of desired data in the cache, and provides these addresses to the CAR. Upon the receipt of a clock signal, the CAR couples the address to the cache memory. The processor includes a data register for receiving accessed cache data over a data bus. Data is latched into the register upon the receipt of a clock signal. Due to inherent delays associated with digital logic comprising the processor, clock signals provided by an external clock are received by the CAR prior to their receipt by the processor's data register. This delay (a fraction of a clock cycle) provides additional time to access the cache memory before the data is expected on the data bus. The CAR is fabricated out of a technology that allows it to drive the address to the large capacitive load of the cache memory in much less time than the processor itself could drive such a load. Thus, due to this buffering capability of the CAR, the cache can be much larger than what could be supported by the processor itself. The time expended sending the address from the processor to the CAR buffer, which would otherwise not be present if the processor addressed the cache directly from an internal register, does not subtract from the processor cycle time since the processor can compute the cache address and send it to the CAR in less than the time required to access the cache.

摘要翻译： 处理器和外部缓存系统之间的改进的接口，具有用于高速计算机系统的特定应用。 用于存储频繁访问的数据的高速缓冲存储器耦合到高速缓存地址寄存器（CAR）。 处理器产生对应于高速缓存中的期望数据的位置的地址，并将这些地址提供给CAR。 在接收到时钟信号时，CAR将地址耦合到高速缓冲存储器。 处理器包括用于通过数据总线接收访问的高速缓存数据的数据寄存器。 在接收到时钟信号时，数据被锁存到寄存器中。 由于与包括处理器的数字逻辑相关联的固有延迟，由外部时钟提供的时钟信号在其被处理器的数据寄存器接收之前由CAR接收。 在数据总线上预期数据之前，这种延迟（一个时钟周期的一小部分）提供了访问高速缓冲存储器的额外时间。 CAR由一种技术制成，允许其在比处理器本身可以驱动这样的负载的时间更短的时间内将地址驱动到高速缓冲存储器的大容性负载。 因此，由于CAR的这种缓冲能力，缓存可以比处理器本身可以支持的大得多。 从处理器发送地址到CAR缓冲区的时间，如果处理器直接从内部寄存器寻址高速缓存，则处理器周期时间不会减少，否则处理器可能不存在地址，因为处理器可以计算缓存地址并发送 它在CAR中少于访问缓存所需的时间。

公开(公告)号：US20240354252A1

公开(公告)日：2024-10-24

申请号：US18634662

申请日：2024-04-12

申请人： MetisX CO., Ltd.

发明人： Do Hun KIM ,  Keebum SHIN ,  Kwangsun LEE

IPC分类号： G06F12/0817 ,  G06F12/0877

CPC分类号： G06F12/0828 ,  G06F12/0877

摘要： It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.

公开(公告)号：US20240296124A1

公开(公告)日：2024-09-05

申请号：US18129559

申请日：2023-03-31

申请人： Micron Technology, Inc.

发明人： Timothy P. Finkbeiner ,  Troy D. Larsen

IPC分类号： G06F12/0877

CPC分类号： G06F12/0877 ,  G06F2212/221 ,  G06F2212/656

摘要： Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.