公开(公告)号：US20170139675A1

公开(公告)日：2017-05-18

申请号：US14939301

申请日：2015-11-12

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  David Raymond LUTZ ,  Christopher Neal HINDS

IPC: G06F7/483

CPC classification number: G06F7/483 ,  G06F7/50 ,  G06F2207/4924

Abstract: Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.

公开(公告)号：US20170139673A1

公开(公告)日：2017-05-18

申请号：US14939175

申请日：2015-11-12

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  David Raymond LUTZ ,  Christopher Neal HINDS

IPC: G06F5/01 ,  G06F7/499 ,  G06F7/483

CPC classification number: G06F5/012 ,  G06F7/483 ,  G06F7/49947 ,  G06F7/50 ,  G06F7/5095 ,  G06F2207/4924

Abstract: A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.

公开(公告)号：US09594557B2

公开(公告)日：2017-03-14

申请号：US15074378

申请日：2016-03-18

Applicant: International Business Machines Corporation

Inventor： Adam J. Muff ,  Paul E. Schardt ,  Robert A. Shearer ,  Matthew R. Tubbs

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/00 ,  G06F7/50 ,  G06F7/483 ,  G06F7/544

CPC classification number: G06F9/3001 ,  G06F7/00 ,  G06F7/483 ,  G06F7/50 ,  G06F7/544 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F9/3895 ,  G06F2207/5442

Abstract: A method provides support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost.

Abstract translation: 一种方法提供对浮点执行单元（例如标量或向量浮点执行单元）中绝对差分运算的压缩和的支持。 可以利用浮点执行单元中的现有加法器以及浮点执行单元中的最小附加逻辑来支持浮点执行单元内的绝对差异指令的固定点压缩和的有效执行，通常不需要单独的 矢量定点执行单元处理器架构，从而导致逻辑和电路面积更少，功耗更低，成本更低。

公开(公告)号：US09582464B2

公开(公告)日：2017-02-28

申请号：US13992229

申请日：2011-12-23

Applicant: Elmoustapha Ould-Ahmed-Vall ,  Mostafa Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Mostafa Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

IPC: G06F7/38 ,  G06F9/302 ,  G06F15/78 ,  G06F9/30 ,  G06F7/544 ,  G06F9/38 ,  G06F7/50

CPC classification number: G06F9/3001 ,  G06F7/50 ,  G06F7/544 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3877 ,  G06F15/78 ,  G06F2207/5442

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.

Abstract translation: 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。

公开(公告)号：US09405535B2

公开(公告)日：2016-08-02

申请号：US13688562

申请日：2012-11-29

Applicant: International Business Machines Corporation

Inventor： Adam J. Muff ,  Paul E. Schardt ,  Robert A. Shearer ,  Matthew R. Tubbs

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/00 ,  G06F7/50

CPC classification number: G06F9/3001 ,  G06F7/00 ,  G06F7/483 ,  G06F7/50 ,  G06F7/544 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F9/3895 ,  G06F2207/5442

Abstract: A circuit arrangement provides support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost.

Abstract translation: 电路装置支持浮点执行单元（例如标量或向量浮点执行单元）中的绝对差分运算的压缩和。 可以利用浮点执行单元中的现有加法器以及浮点执行单元中的最小附加逻辑来支持浮点执行单元内的绝对差异指令的固定点压缩和的有效执行，通常不需要单独的 矢量定点执行单元处理器架构，从而导致逻辑和电路面积更少，功耗更低，成本更低。

公开(公告)号：US20130268571A1

公开(公告)日：2013-10-10

申请号：US13442169

申请日：2012-04-09

Applicant: Gil Naveh

Inventor： Gil Naveh

IPC: G06F17/10 ,  G06F7/50 ,  G06F7/52

CPC classification number: G06F7/50 ,  G06F7/52 ,  G06F17/10 ,  H04M7/129 ,  H04M7/1295 ,  H04Q1/4575

Abstract: An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a second value at least in part by multiplying each of a portion of the samples by respective ones of a second set of values for the impulse response and summing the results. The data processing system is operative to determine the power of the tone in the multiple samples of the input signal at least in part by utilizing the first value and the second value.

Abstract translation: 用于确定输入信号中存在音调的装置包括耦合到存储器电路的存储器电路和数据处理电路。 数据处理电路可操作以接收输入信号的多个样本，并且至少部分地通过将每个样本乘以用于脉冲响应的第一组值的相应值并将结果相加来确定第一值。 所述数据处理系统还可操作以至少部分地通过将所述样本的每一个乘以脉冲响应的第二组值并将结果相加来确定第二值。 数据处理系统至少部分地通过利用第一值和第二值来确定输入信号的多个样本中的音调的功率。

公开(公告)号：US20130238680A1

公开(公告)日：2013-09-12

申请号：US13873517

申请日：2013-04-30

Applicant: FUJITSU LIMITED

Inventor： Hiroaki ATSUMI

IPC: G06F7/544

CPC classification number: G06F7/544 ,  G06F7/493 ,  G06F7/50

Abstract: A decimal absolute value adder includes a first circuit adding two operands for a first result; a second circuit adding the two operands to 10 for a second result; a third circuit adding the two operands to 6 for a third result; a fourth circuit adding the two operands to 1 for a fourth result; a fifth circuit adding the two operands to 11 for a fifth result; a sixth circuit adding the two operands to 7 for a sixth result; and a selection circuit selecting the first, second, fourth or fifth result when adding two numbers of identical signs or adding two numbers of different signs resulting in a non-negative result, and selecting a 1's complement of the first, third, fourth or sixth result when adding two numbers of different signs resulting in a negative result.

Abstract translation: 十进制绝对值加法器包括对第一结果添加两个操作数的第一电路; 第二电路将两个操作数加到10以获得第二结果; 第三个电路将两个操作数添加到6，获得第三个结果; 第四个电路将两个操作数添加到第一个结果; 第五个电路将两个操作数添加到第十个结果的11个; 第六个电路将两个操作数添加到第七个结果; 以及选择电路，当添加两个数目相同的符号时，选择第一，第二，第四或第五结果，或者添加两个不同的符号，导致非负结果，并且选择第一，第三，第四或第六 当添加两个数字的不同符号导致负面结果时，结果。

公开(公告)号：US08037120B2

公开(公告)日：2011-10-11

申请号：US11566692

申请日：2006-12-05

Applicant: Abhijit Giri

Inventor： Abhijit Giri

IPC: G06F7/50 ,  G06F7/00 ,  G06F15/00

CPC classification number: G06F7/026 ,  G06F7/02 ,  G06F7/50

Abstract: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N−1:0] and a second N-bit vector B[N−1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N−1:0] & ˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N−1:0]^˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. The difference between the first N-bit vector A[N−1:0] and the second N-bit vector B[N−1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m

Abstract translation: 一种改进的技术，显着地减少了用于确定两个多位向量之间的差异是否等于给定数目或位于数字逻辑电路中的给定两个数之间的所需逻辑和计算时间。 在一个示例实施例中，这通过在数字逻辑电路中接收第一N位向量A [N-1：0]和第二N位向量B [N-1：0]来实现，其中N是非 - 零正数。 然后通过使用A [N-1：0]和〜B [N-1：0]进行逐位AND（A [N-1：0]＆〜B [N-1：0]）操作获得第三N比特向量 N-1：0]。 此外，通过使用A [N-1：0]和〜B来执行逐位XOR（A [N-1：0] ^〜B [N-1：0]）操作来获得第四N比特向量 [N-1：0]。 然后将第一N位向量A [N-1：0]和第二N位向量B [N-1：0]之间的差被声明为等于给定数或在给定的范围内 数字（+ m和+ n，m

公开(公告)号：US20080133628A1

公开(公告)日：2008-06-05

申请号：US11566692

申请日：2006-12-05

Applicant: ABHIJIT GIRI

Inventor： ABHIJIT GIRI

IPC: G06F7/38

CPC classification number: G06F7/026 ,  G06F7/02 ,  G06F7/50

Abstract: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A[N−1:0] and a second N-bit vector B[N−1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N−1:0] & ˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N−1:0]̂˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. The difference between the first N-bit vector A[N−1:0] and the second N-bit vector B[N−1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m

Abstract translation: 一种改进的技术，显着地减少了用于确定两个多位向量之间的差异是否等于给定数目或位于数字逻辑电路中的给定两个数之间的所需逻辑和计算时间。 在一个示例实施例中，这通过在数字逻辑电路中接收第一N位向量A [N-1：0]和第二N位向量B [N-1：0]来实现，其中N是非 - 零正数。 然后通过使用A [N-1：0]和〜B [N-1：0]进行逐位AND（A [N-1：0]＆〜B [N-1：0]）操作获得第三N比特向量 N-1：0]。 此外，通过使用A [N-1：0]和〜B来执行逐位XOR（A [N-1：0]〜B [N-1：0]）操作来获得第四N位向量 [N-1：0]。 然后将第一N位向量A [N-1：0]和第二N位向量B [N-1：0]之间的差被声明为等于给定数或在给定的范围内 数字（+ m和+ n，m

公开(公告)号：US06870090B2

公开(公告)日：2005-03-22

申请号：US10109819

申请日：2002-03-28

Applicant: Dakshi Agrawal ,  Bruce Roy Archambeault ,  Josyula R. Rao ,  Pankaj Rohatgi

Inventor： Dakshi Agrawal ,  Bruce Roy Archambeault ,  Josyula R. Rao ,  Pankaj Rohatgi

IPC: G06F7/50 ,  G06F21/00 ,  H05K9/00

CPC classification number: G06F21/75 ,  G06F7/50 ,  G06F21/556 ,  G06F2207/7219

Abstract: An electronic device for distorting sensitive information in one or more electromagnetic emanations from the electronic device is disclosed. The device has one or more active layers having one or more electronic components that emit the electromagnetic emanations and one or more conductive substrate layers planarity adjacent to one or more of the active layers that distort the electromagnetic emanations. In alternative embodiments of the inventions, shielding is added with frequency selective openings. In other alternative embodiments, a signal source is added to distort sensitive information.

Abstract translation: 公开了一种用于使来自电子设备的一个或多个电磁辐射中的敏感信息变形的电子设备。 该器件具有一个或多个有源层，其具有发射电磁发射的一个或多个电子元件，以及一个或多个导电衬底层与一个或多个有源层相邻的平面性，使电磁辐射失真。 在本发明的替代实施例中，屏蔽被添加有频率选择性开口。 在其他替代实施例中，添加信号源以扭曲敏感信息。