公开(公告)号：US4725982A

公开(公告)日：1988-02-16

申请号：US845540

申请日：1986-03-28

申请人： Hiroyuki Hara ,  Yasuhiro Sugimoto

发明人： Hiroyuki Hara ,  Yasuhiro Sugimoto

IPC分类号： H03K19/0175 ,  H01L21/8249 ,  H01L27/06 ,  H03K19/082 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0952 ,  G11C11/34 ,  G11C7/00 ,  G11C11/56 ,  H01L27/02

CPC分类号： H03K19/09425 ,  H03K19/0826 ,  H03K19/09448

摘要： A tri-state buffer circuit according to the present invention comprises a switching circuit connected to an input terminal (IN), tri-state and inverted tri-state input terminals (T, T), and a first power supply terminal for generating first and second switching signals (A, B) which have a first and second levels, respectively, only when the tri-state signal is on a first level, regardless the level of the input signal; an inverter circuit connected to said switching circuit, and the first power supply terminal for inverting the first switching signal (A) from said switching circuit as an output signal; a selection circuit connected to said switching circuit and inverter circuit for maintaining a signal, which have a second level, equal to the inverted signal only when the tri-state signal is on first level; a first type bipolar transistor whose base is connected to said inverter circuit, whose collecter is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and a first type bipolar transister whose base is connected to said selection circuit, whose collecter is connected to the output terminal of the tri-state circuit, and whose emitter is connected to a second power supply terminal.

摘要翻译： 根据本发明的三态缓冲电路包括连接到输入端（IN），三态和反相三态输入端（T，＆amp; T和T）的开关电路和用于产生第一 和仅在三态信号处于第一电平时分别具有第一和第二电平的第二开关信号（A，B），而与输入信号的电平无关; 连接到所述开关电路的逆变器电路和用于将来自所述开关电路的所述第一开关信号（A）反相作为输出信号的所述第一电源端子; 连接到所述开关电路和逆变器电路的选择电路，用于仅在三态信号处于第一电平时保持具有等于反相信号的第二电平的信号; 第一型双极晶体管，其基极连接到所述逆变器电路，其集电器连接到第一电源端子，并且其发射极连接到三态电路的输出端子; 以及第一型双极转移器，其基极连接到所述选择电路，其集电器连接到三态电路的输出端，并且其发射极连接到第二电源端子。

公开(公告)号：US4587446A

公开(公告)日：1986-05-06

申请号：US499704

申请日：1983-05-31

申请人： Koichiro Okumura

发明人： Koichiro Okumura

IPC分类号： H03K19/0175 ,  H03K19/017 ,  H03K19/094 ,  H03K17/693

CPC分类号： H03K19/01714 ,  H03K19/09425 ,  H03K19/09429

摘要： An output circuit which can operate at a high-speed and with a small power consumption is disclosed. The output circuit comprises a first series circuit including first and second transistors, an intermediate junction of the first and second transistors being connected to an output terminal, an impedance means, means for connecting one end of the impedance means to a power voltage terminal, and a third transistor connected between the other end of the impedance means to a second voltage terminal, one and the other ends of the impedance means being connected to control electrodes of the second and first transistors, respectively.

摘要翻译： 公开了一种可以高速且功耗小的输出电路。 输出电路包括第一串联电路，包括第一和第二晶体管，第一和第二晶体管的中间结连接到输出端，阻抗装置，用于将阻抗装置的一端连接到电源电压端子的装置，以及 连接在阻抗装置的另一端之间的第三晶体管与第二电压端子，阻抗装置的一端和另一端分别连接到第二和第一晶体管的控制电极。

公开(公告)号：US4533841A

公开(公告)日：1985-08-06

申请号：US414832

申请日：1982-09-03

申请人： Satoshi Konishi

发明人： Satoshi Konishi

IPC分类号： H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K19/21 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K19/09425 ,  H03K19/09443 ,  H03K19/09445 ,  H03K19/0948 ,  H03K19/215

摘要： A MOS logic circuit including a known MOS logic circuit arrangement having a particular input/output signal transfer characteristic and a control gating circuit including an FET connected to the known MOS logic circuit arrangement, the gate of which gating circuit receives a control voltage derived from an irreversible control voltage generator utilizing a fuse. Under the control of the irreversible control voltage, the MOS logic circuit can permanently change the known logic circuit arrangement's signal transfer characteristic without varying its logic function.

摘要翻译： 包括具有特定输入/输出信号传递特性的已知MOS逻辑电路装置和包括连接到已知MOS逻辑电路装置的FET的控制选通电路的MOS逻辑电路，门控电路接收来自 使用保险丝的不可逆控制电压发生器。 在不可逆控制电压的控制下，MOS逻辑电路可以永久地改变已知逻辑电路布置的信号传递特性而不改变其逻辑功能。

公开(公告)号：US4518875A

公开(公告)日：1985-05-21

申请号：US534269

申请日：1983-09-22

申请人： Haluk M. Aytac

发明人： Haluk M. Aytac

IPC分类号： H03K19/094 ,  H03K19/0948 ,  H03K19/20

CPC分类号： H03K19/09482 ,  H03K19/09425

摘要： A ternary logic circuit comprises a load element connected to one voltage level and to a node and a logic section connected to a second voltage level and the same node from which the circuit output is derived. The two voltage levels including the voltage supply and ground voltage enable the circuit to provide an output at three logic levels, "0", "1", and "2", depending on inputs to the logic section. The circuit may be implemented with CMOS technology using, in addition, N-channel or P-channel depletion devices, in different logic formats such as ternary extensions of NAND or NOR gate circuits with the logic section elements arranged in different configurations and combinations of pairs of CMOS devices.

摘要翻译： 三元逻辑电路包括连接到一个电压电平的负载元件和连接到第二电压电平的节点和逻辑部分以及从其导出电路输出的相同节点。 包括电压源和地电压的两个电压电平使电路能够根据逻辑部分的输入，提供三个逻辑电平“0”，“1”和“2”的输出。 该电路可以使用CMOS技术，另外使用不同逻辑格式的N沟道或P沟道耗尽装置，例如NAND或NOR门电路的三进制扩展，其中逻辑部分元件以不同的配置和对的组合排列 的CMOS器件。

公开(公告)号：US4491749A

公开(公告)日：1985-01-01

申请号：US477897

申请日：1983-03-23

申请人： Jun Iwamura

发明人： Jun Iwamura

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/082

CPC分类号： H03K19/09425 ,  H03K19/09429

摘要： A three-output level logic circuit comprises an output stage and a drive stage for driving the output stage. The output stage includes first and second MOS transistors connected in series between first and second power sources and a terminal is provided for producing three-state output signals. The drive stage includes third to sixth MOS transistors connected in series between the first and second power sources. A terminal is provided for supplying a data signal to the fourth and fifth MOS transistors. A control signal is supplied in common to the gate electrodes of the third to sixth MOS transistors. The conductivity types of the first to sixth MOS transistors are selected to operate the logic circuit with one control signal input and one data signal input.

摘要翻译： 三输出电平逻辑电路包括用于驱动输出级的输出级和驱动级。 输出级包括在第一和第二电源之间串联连接的第一和第二MOS晶体管，并且提供用于产生三态输出信号的端子。 驱动级包括串联连接在第一和第二电源之间的第三至第六MOS晶体管。 提供一个用于向第四和第五MOS晶体管提供数据信号的端子。 控制信号被共同地提供给第三至第六MOS晶体管的栅电极。 选择第一至第六MOS晶体管的导电类型来操作具有一个控制信号输入和一个数据信号输入的逻辑电路。

公开(公告)号：US4408135A

公开(公告)日：1983-10-04

申请号：US216818

申请日：1980-12-16

申请人： Toshio Yuyama ,  Ryuzo Shiraki ,  Seizi Watanabe

发明人： Toshio Yuyama ,  Ryuzo Shiraki ,  Seizi Watanabe

IPC分类号： H03K5/02 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K5/023 ,  H03K17/6872 ,  H03K19/09425

摘要： A multi-level signal generating circuit is disclosed which comprises: a first CMOS inverter for inverting an input signal to produce a first output signal having high and low voltage levels; a second CMOS inverter for inverting the input signal to produce a second output signal having high and low voltage levels; at least one of the high and low voltage levels of the second output signals being different from said high and low voltage of said first output signal; and switching circuit operative to drive selectively said first CMOS inverter or said second CMOS inverter in response to a level of a control signal.

摘要翻译： 公开了一种多电平信号发生电路，其包括：第一CMOS反相器，用于反相输入信号以产生具有高和低电压电平的第一输出信号; 第二CMOS反相器，用于反相输入信号以产生具有高和低电压电平的第二输出信号; 所述第二输出信号的所述高电压和低电压电平中的至少一个与所述第一输出信号的所述高电压和低电压不同; 以及切换电路，用于响应于控制信号的电平而有选择地驱动所述第一CMOS反相器或所述第二CMOS反相器。

公开(公告)号：US4363978A

公开(公告)日：1982-12-14

申请号：US174089

申请日：1980-07-31

申请人： Gary L. Heimbigner

发明人： Gary L. Heimbigner

IPC分类号： H03K19/0175 ,  H03K5/02 ,  H03K19/00 ,  H03K19/094 ,  H03K19/092 ,  H03K3/26

CPC分类号： H03K5/023 ,  H03K19/0016 ,  H03K19/09425 ,  H03K19/09429

摘要： A tristate driver circuit is provided having a logic input signal, to produce a logic 1 output level or a logic 0 output level, and a float input signal, to produce float state operation. The circuit comprises a first logic gate powered by a first buffer switch, a second logic gate powered by a second buffer switch, an output driver having a first driver input from the output of the first gate and a second signal driver input from the output of the second gate; the first and second buffer switches dissipating the greatest circuit power during the circuit float state operation, and means, coupled to the first and second buffer switches and to the source of float signal input signal, for interrupting power to the first and second buffer switches responsive to onset of the float state operation.

摘要翻译： 提供具有逻辑输入信号以产生逻辑1输出电平或逻辑0输出电平的三态驱动器电路和浮动输入信号，以产生浮置状态操作。 电路包括由第一缓冲开关供电的第一逻辑门，由第二缓冲开关供电的第二逻辑门，具有来自第一门输出的第一驱动器输入的输出驱动器和从第一门的输出输入的第二信号驱动器 第二门 第一和第二缓冲器开关在电路浮动状态操作期间耗散最大电路功率，以及耦合到第一和第二缓冲器开关和浮动信号输入信号源的装置，用于中断对第一和第二缓冲器开关的电力响应 开始浮动状态操作。

公开(公告)号：US20240204782A1

公开(公告)日：2024-06-20

申请号：US18081907

申请日：2022-12-15

申请人： Intel Corporation

发明人： Amit Agarwal ,  Steven K. Hsu ,  Ram Kumar Krishnamurthy

IPC分类号： H03K19/094 ,  H03K19/017 ,  H03K19/1776

CPC分类号： H03K19/09425 ,  H03K19/01728 ,  H03K19/1776

摘要： Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.

公开(公告)号：US09674015B2

公开(公告)日：2017-06-06

申请号：US14798364

申请日：2015-07-13

申请人： Xilinx, Inc.

发明人： Vassili Kireev ,  Yu Liao

IPC分类号： H04L25/49 ,  H03K5/24 ,  H03K19/094 ,  H03K19/177

CPC分类号： H04L25/4919 ,  H03K5/2481 ,  H03K19/09425 ,  H03K19/17788 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/4917

摘要： A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

公开(公告)号：US20150236695A1

公开(公告)日：2015-08-20

申请号：US14703483

申请日：2015-05-04

申请人： Wave Semiconductor, Inc.

发明人： Gajendra Prasad Singh

IPC分类号： H03K19/00 ,  H03K19/094

CPC分类号： H03K19/0013 ,  H03K19/094 ,  H03K19/09425 ,  H03K19/096 ,  H03K19/23 ,  H03K23/40 ,  H03K23/58

摘要： Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

摘要翻译： 多阈值闪存Null Convention Logic（NCL）在闪存NCL门内包括一个或多个高阈值电压晶体管，以减少由NCL门晶体管的电流泄漏引起的功耗。 可以添加高阈值电压晶体管和/或可以代替NCL门的一个或多个低电压阈值晶体管。 上拉路径中包含高Vt器件，以在闪存NCL逻辑门处于空状态时降低功耗。