公开(公告)号：US06180989B2

公开(公告)日：2001-01-30

申请号：US09144182

申请日：1998-08-31

申请人： Frank R. Bryant ,  Danielle A. Thomas

发明人： Frank R. Bryant ,  Danielle A. Thomas

IPC分类号： H01L2982

CPC分类号： G06K9/00053 ,  Y10S438/931 ,  Y10S438/953 ,  Y10S438/958

摘要： A structure and method for creating an integrated circuit passivation structure comprising, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

摘要翻译： 一种用于产生集成电路钝化结构的结构和方法，包括：电路，电介质和金属板，其上设置有电隔离电路的绝缘层，以及沉积以形成钝化结构的放电层， 公开了由例如手指引起的静电放电的电路。 放电层还包含选择性沉积的掺杂剂以增加静电放电承载能力，同时保持总感测分辨率。

公开(公告)号：US06146936A

公开(公告)日：2000-11-14

申请号：US210257

申请日：1998-12-11

申请人： H. Montgomery Manning

发明人： H. Montgomery Manning

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/8234

CPC分类号： H01L27/11 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/923 ,  Y10S438/953

摘要： The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method comprising: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device. In another aspect, the invention includes a method comprising: a) providing a semiconductor substrate; b) defining an SRAM cell pull-down device region of the semiconductor substrate, the pull-down device region comprising a pull-down device source region and a pull-down device drain region; c) defining an SRAM access device source region and an access device drain region; d) defining a field oxide isolation region of the semiconductor substrate; and e) in a common implant, implanting a conductivity-enhancing dopant of a first conductivity type beneath the field oxide region, beneath the access device source region, and beneath the pull-down device drain region; the common implant not implanting the conductivity-enhancing dopant of the first conductivity type beneath at least one of the access device drain region and the pull-down device source region.

摘要翻译： 本发明涉及形成集成电路的方法，形成SRAM单元的方法，以及减少对SRAM单元的α粒子造成的损害的方法。 另外，本发明涉及集成电路。 一方面，本发明包括一种方法，包括：a）在第一导电类型的SRAM单元下拉器件漏极和第一导电类型的SRAM单元访问器件源之间的至少一个下面形成至少一个第二导电类型扩散区域 导电型; 以及b）在所述SRAM单元下拉器件的源极和所述SRAM单元存取器件的漏极中的至少一个之下，不形成第二导电型扩散区域。 另一方面，本发明包括一种方法，包括：a）提供半导体衬底; b）限定半导体衬底的SRAM单元下拉器件区域，所述下拉器件区域包括下拉器件源极区域和下拉器件漏极区域; c）限定SRAM访问设备源区域和接入设备漏极区域; d）限定半导体衬底的场氧化物隔离区; 和e）在公共注入中，在所述场氧化物区域下方，在所述进入装置源区域下方以及所述下拉装置漏极区域下方注入第一导电类型的导电性增强掺杂剂; 所述普通植入物不将所述第一导电类型的电导率增强掺杂剂植入到所述进入器件漏极区域和所述下拉器件源极区域中的至少一个之下。

公开(公告)号：US6091082A

公开(公告)日：2000-07-18

申请号：US024094

申请日：1998-02-17

申请人： Danielle A. Thomas ,  Frank Randolph Bryant

发明人： Danielle A. Thomas ,  Frank Randolph Bryant

IPC分类号： G06K9/00

CPC分类号： G06K9/00053 ,  Y10S438/931 ,  Y10S438/953 ,  Y10S438/958

摘要： A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

公开(公告)号：US5973369A

公开(公告)日：1999-10-26

申请号：US816038

申请日：1997-03-11

申请人： Fumihiko Hayashi

发明人： Fumihiko Hayashi

IPC分类号： H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S438/953

摘要： A memory cell for a semiconductor device includes two pairs of a transfer transistor and a drive transistor at a first level and a pair of load transistors above the two pairs of transfer and drive transistors at a second level. Each of the load transistors includes a gate, a source/drain, and a channel. The cell further includes a pair of contacts extending between the first and second levels and that connect one of the gates to a respective one of the two pairs of transfer and drive transistors. Each load transistor gate includes a portion that overlies its respective channel and a lateral extension therefrom that contacts a respective one of the contacts. The extension of one load transistor gate overlaps the source/drain of the other load transistor adjacent the respective one of the contacts.

摘要翻译： 用于半导体器件的存储单元包括两对传输晶体管和处于第二电平的两对传输和驱动晶体管的第一级的驱动晶体管和一对负载晶体管。 每个负载晶体管包括栅极，源极/漏极和沟道。 电池还包括在第一和第二电平之间延伸的一对触点，并且将一个栅极连接到两对传输和驱动晶体管中的相应一个。 每个负载晶体管栅极包括覆盖其相应通道的部分和与其相应的触点之间的横向延伸部分。 一个负载晶体管栅极的延伸与另一个负载晶体管的源极/漏极重叠在相邻的一个触点附近。

公开(公告)号：US5889316A

公开(公告)日：1999-03-30

申请号：US595266

申请日：1996-02-01

申请人： David J. Strobel ,  David R. Czajkowski

发明人： David J. Strobel ,  David R. Czajkowski

IPC分类号： G21F1/08 ,  G21F3/00 ,  H01L23/552 ,  H01L27/02 ,  H01L23/28

CPC分类号： H01L23/552 ,  G21F1/08 ,  G21F3/00 ,  H01L27/02 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10S257/921 ,  Y10S438/953

摘要： A new and improved process by which plastic material forming the plastic body package of an integrated circuit is selectively removed and replaced with a radiation shield having a specific formulation that is customized for a given radiation environment dependent upon the space application in which the integrated circuit is to be used.

摘要翻译： 选择性地移除形成集成电路的塑料主体封装的塑料材料的新的和改进的过程，并且用具有针对给定辐射环境定制的特定配方的辐射屏蔽替代，这取决于集成电路的空间应用 要使用的。

公开(公告)号：US5877051A

公开(公告)日：1999-03-02

申请号：US917450

申请日：1997-08-22

申请人： H. Montgomery Manning

发明人： H. Montgomery Manning

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/8234

CPC分类号： H01L27/11 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/923 ,  Y10S438/953

摘要： The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method which includes: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device. In another aspect, the invention includes a method which includes a) providing a semiconductor substrate; b) defining an SRAM cell pull-down device region of the semiconductor substrate, the pull-down device region having a pull-down device source region and a pull-down device drain region; c) defining an SRAM access device source region and an access device drain region; d) defining a field oxide isolation region of the semiconductor substrate; and e) in a common implant, implanting a conductivity-enhancing dopant of a first conductivity type beneath the field oxide region, beneath the access device source region, and beneath the pull-down device drain region; the common implant not implanting the conductivity-enhancing dopant of the first conductivity type beneath at least one of the access device drain region and the pull-down device source region.

摘要翻译： 本发明涉及形成集成电路的方法，形成SRAM单元的方法，以及减少对SRAM单元的α粒子造成的损害的方法。 另外，本发明涉及集成电路。 一方面，本发明包括一种方法，其包括：a）在第一导电类型的SRAM单元下拉器件漏极和SRAM单元访问器件源之间的至少一个下形成至少一个第二导电类型扩散区域 第一导电类型; 以及b）在所述SRAM单元下拉器件的源极和所述SRAM单元存取器件的漏极中的至少一个之下，不形成第二导电型扩散区域。 另一方面，本发明包括一种方法，其包括：a）提供半导体衬底; b）限定半导体衬底的SRAM单元下拉器件区域，所述下拉器件区域具有下拉器件源极区域和下拉器件漏极区域; c）限定SRAM访问设备源区域和接入设备漏极区域; d）限定半导体衬底的场氧化物隔离区; 和e）在公共注入中，在所述场氧化物区域下方，在所述进入装置源区域下方以及所述下拉装置漏极区域下方注入第一导电类型的导电性增强掺杂剂; 所述普通植入物不将所述第一导电类型的电导率增强掺杂剂植入到所述进入器件漏极区域和所述下拉器件源极区域中的至少一个之下。

公开(公告)号：US5681769A

公开(公告)日：1997-10-28

申请号：US482338

申请日：1995-06-06

申请人： Chuen-Der Lien

发明人： Chuen-Der Lien

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L27/11 ,  H01L29/4238 ,  H01L29/7833 ,  Y10S257/903 ,  Y10S438/953

摘要： A high capacitance field effect transistor for use in an integrated memory circuit is fabricated with an optimized gate electrode and active region overlap, increasing the gate electrode to substrate capacitance thereby minimizing the effect of alpha particle upset. The optimized overlap is accomplished by maximizing the opening in the field oxide layer which defines the active region. In some embodiments, the transistor is also optimized for overall cell layout area.

摘要翻译： 制造用于集成存储器电路的高电容场效应晶体管，其具有优化的栅电极和有源区重叠，从而将栅电极增加到衬底电容，从而最小化α粒子扰乱的影响。 优化的重叠通过使定义有源区域的场氧化物层中的开口最大化来实现。 在一些实施例中，晶体管还针对整体单元布局区域进行优化。

公开(公告)号：US5670413A

公开(公告)日：1997-09-23

申请号：US586556

申请日：1996-01-16

申请人： Robert T. Fuller

发明人： Robert T. Fuller

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76235 ,  Y10S438/953

摘要： A radiation hardening isolation technique uses a poly buffered LOCOS structure (34, 36) to protect the device areas during field oxide 40 formation. The field oxide 40 is removed, and the polysilicon structure 34 is covered with a PSG or BPSG layer 42. Layer 42 is planarized and the polysilicon 34 is removed to provide a self-aligned device region 31.

摘要翻译： 放射硬化隔离技术使用多重缓冲LOCOS结构（34,36）来保护场氧化物40形成期间的器件区域。 去除场氧化物40，多晶硅结构34被PSG或BPSG层42覆盖。层42被平坦化，多晶硅34被去除以提供自对准器件区域31。

公开(公告)号：US5137837A

公开(公告)日：1992-08-11

申请号：US569304

申请日：1990-08-20

申请人： Chen-Chi P. Chang ,  Mei F. Li

发明人： Chen-Chi P. Chang ,  Mei F. Li

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/76264 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L21/76267 ,  H01L21/76281 ,  Y10S438/953

摘要： Highly doped N- and P-type wells (16a, 16b) in a first silicon layer (16) on an insulator layer (14) of a SIMOX substrate (10). Complementary MOSFET devices (52,54,58,62) are formed in lightly doped N- and P-type active areas (22a, 22b) in a second silicon layer (22) formed on the first silicon layer (16). Adjacent active areas (22a, 22b) and underlying wells (16a, 16b) are isolated from each other by trenches (36,78) filled with a radiation-hard insulator material. Field oxide layers (42,64) are formed of a radiation-hard insulator material, preferably boron phosphorous silicon dioxide glass, over the surface of the second silicon layer (22) except in contact areas (68) of the devices (52,54,58,62). The devices (52,54,58,62) are formed in the upper portions of the active areas (22a, 22b), and are insensitive to the interfacial states of the SIMOX substrate (10). The buried wells (16a, 16b ) under the active areas (22a, 22b) have low resistance and enable the devices (52,54,58,62) to have high snap-back voltages. The absence of sharp edges also eliminates edge leakage upon high dosage irradiation, thus producing devices that are more radiation-resistant.

摘要翻译： 在SIMOX基板（10）的绝缘体层（14）上的第一硅层（16）中的高掺杂的N和P型阱（16a，16b）。 互补MOSFET器件（52,54,58,62）形成在形成在第一硅层（16）上的第二硅层（22）中的轻掺杂的N和P型有源区（22a，22b）中。 相邻的有源区域（22a，22b）和下面的阱（16a，16b）通过填充有辐射 - 硬质绝缘体材料的沟槽（36,78）彼此隔离。 在第二硅层（22）的表面上除了装置（52,54）的接触区域（68）之外，场氧化物层（42,64）由辐射 - 硬的绝缘体材料，优选为二氧化硅磷玻璃制成， ，58,62）。 器件（52,54,58,62）形成在有源区（22a，22b）的上部，并且对SIMOX衬底（10）的界面状态不敏感。 有源区（22a，22b）下面的埋置阱（16a，16b）具有低电阻，并使得器件（52,54,58,62）能够具有高的快速恢复电压。 没有锋利的边缘也消除了高剂量照射时的边缘泄漏，从而产生更耐辐射的装置。

公开(公告)号：US5026656A

公开(公告)日：1991-06-25

申请号：US488360

申请日：1990-03-02

申请人： Mishel Matloubian ,  Cheng-Eng D. Chen ,  Terence G. Blake

发明人： Mishel Matloubian ,  Cheng-Eng D. Chen ,  Terence G. Blake

IPC分类号： H01L21/74 ,  H01L23/482 ,  H01L29/786

CPC分类号： H01L23/4825 ,  H01L21/743 ,  H01L29/78609 ,  H01L29/78612 ,  H01L2924/0002 ,  Y10S438/953

摘要： An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

摘要翻译： 公开了一种MOS晶体管，其具有用于在暴露于电离辐射之后通过隔离氧化物防止源极至漏极导通的保护环。 在所描述的n沟道晶体管的例子中，相对于栅电极以自对准的方式在源极区域的边缘处形成p +区域，以便不在栅极下方延伸以接触漏极区域。 即使在栅电极与场氧化物重叠的隔离场氧化物下面形成沟道，该p +区形成二极管，其阻止源 - 漏导通。 该结构可以被硅化以提高串联电阻。 还公开了以SOI配置形成的晶体管的示例。