公开(公告)号：US07157290B2

公开(公告)日：2007-01-02

申请号：US10980178

申请日：2004-11-04

申请人： Brett J. Hamilton

发明人： Brett J. Hamilton

IPC分类号： H01L21/00

CPC分类号： H05K9/00 ,  H05K1/0233 ,  H05K1/165 ,  H05K2201/10265 ,  H05K2201/10689 ,  H05K2203/304 ,  Y10S438/953

摘要： A magnetically shielded circuit board having a conductive solenoid to repel high speed charged particles away from an integrated circuit chip. The conductive solenoid is embedded in the circuit board, or located around the circuit board, or located within an integrated circuit package, the integrated circuit package have been connected to the circuit board. The conductive solenoid is used for conducting an electrical current, the electrical current forming a magnetic field. The magnetic field will repel high speed charged particles away from the integrated circuit chip, the integrated circuit chip being within the integrated circuit package. The circuit board can be used in a space vehicle.

摘要翻译： 一种具有导电螺线管的磁屏蔽电路板，用于将高速带电粒子排斥离开集成电路芯片。 导电螺线管嵌入在电路板中，或者位于电路板周围，或者位于集成电路封装内，集成电路封装已经连接到电路板。 导电螺线管用于传导电流，电流形成磁场。 磁场将排斥高速带电粒子远离集成电路芯片，集成电路芯片在集成电路封装内。 电路板可用于太空车。

公开(公告)号：US20050064607A1

公开(公告)日：2005-03-24

申请号：US10980178

申请日：2004-11-04

申请人： Brett Hamilton

发明人： Brett Hamilton

IPC分类号： H01L21/00 ,  H01L23/04 ,  H01L23/52 ,  H01L29/00 ,  H01L29/82 ,  H01L43/00 ,  H05K1/02 ,  H05K1/16 ,  H05K9/00

CPC分类号： H05K9/00 ,  H05K1/0233 ,  H05K1/165 ,  H05K2201/10265 ,  H05K2201/10689 ,  H05K2203/304 ,  Y10S438/953

摘要： A magnetically shielded circuit board having a conductive solenoid to repel high speed charged particles away from an integrated circuit chip. The conductive solenoid is embedded in the circuit board, or located around the circuit board, or located within an integrated circuit package, the integrated circuit package have been connected to the circuit board. The conductive solenoid is used for conducting an electrical current, the electrical current forming a magnetic field. The magnetic field will repel high speed charged particles away from the integrated circuit chip, the integrated circuit chip being within the integrated circuit package. The circuit board can be used in a space vehicle.

摘要翻译： 一种具有导电螺线管的磁屏蔽电路板，用于将高速带电粒子排斥离开集成电路芯片。 导电螺线管嵌入在电路板中，或者位于电路板周围，或者位于集成电路封装内，集成电路封装已经连接到电路板。 导电螺线管用于传导电流，电流形成磁场。 磁场将排斥高速带电粒子远离集成电路芯片，集成电路芯片在集成电路封装内。 电路板可用于太空车。

公开(公告)号：US06833559B2

公开(公告)日：2004-12-21

申请号：US10660602

申请日：2003-09-12

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L2904

CPC分类号： H01L45/1658 ,  H01C17/075 ,  H01C17/288 ,  H01L27/24 ,  H01L29/685 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/942 ,  Y10S438/953

摘要： A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein. An actinic energy blocking material layer is formed on the conductive electrode material, the actinic energy blocking material layer being effective to shield actinic energy from reaching an interface of the conductive electrode material and the actinic energy blocking material to substantially preclude diffusion of the conductive electrode material into the chalcogenide material upon exposure to said actinic energy. A dielectric layer is formed on the actinic energy blocking material layer. The conductive electrode material is formed into a first electrode. A second electrode is provided proximate the chalcogenide material having the metal diffused therein. Non-volatile resistance variable devices manufacture by these and other methods are contemplated.

摘要翻译： 在暴露于能够使金属扩散到硫族化物材料中的光化能的量子时，排除金属扩散到相邻硫族化物材料中的方法包括在金属上形成光化能量阻挡材料层至厚度不大于500 然后将光化性能量阻挡材料层暴露于所述光化能量级。 在一个实施方案中，在金属上形成均匀的光化能阻挡材料层，随后暴露于所述光化能量级。 形成非易失性电阻可变器件的方法包括在其中扩散金属离子的硫族化物材料上提供导电电极材料。 在导电电极材料上形成光化学能量阻挡材料层，光化学能量阻挡材料层有效地屏蔽光化能到达导电电极材料和光化能阻挡材料的界面，从而基本排除导电电极材料的扩散 在暴露于所述光化能之后进入硫族化物材料。 在光化能阻挡材料层上形成介电层。 导电电极材料形成为第一电极。 靠近硫属化物材料设置第二电极，其中金属在其中扩散。 考虑通过这些和其他方法制造的非易失性电阻可变器件。

公开(公告)号：US06610555B1

公开(公告)日：2003-08-26

申请号：US09724847

申请日：2000-11-28

申请人： Frank R. Bryant ,  Danielle A. Thomas

发明人： Frank R. Bryant ,  Danielle A. Thomas

IPC分类号： H01L2100

CPC分类号： G06K9/00053 ,  Y10S438/931 ,  Y10S438/953 ,  Y10S438/958

摘要： A structure and method for creating an integrated circuit passivation structure including, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

摘要翻译： 一种用于产生集成电路钝化结构的结构和方法，该集成电路钝化结构包括：电路，电介质和金属板，在该绝缘层上设置电绝缘电路的绝缘层，以及沉积以形成钝化结构的放电层， 公开了由例如手指引起的静电放电的电路。 放电层还包含选择性沉积的掺杂剂以增加静电放电承载能力，同时保持总感测分辨率。

公开(公告)号：US5561319A

公开(公告)日：1996-10-01

申请号：US298041

申请日：1994-08-30

申请人： Alexander H. Owens ,  Shahin Toutounchi ,  Abraham Yee ,  Michael Lyu

发明人： Alexander H. Owens ,  Shahin Toutounchi ,  Abraham Yee ,  Michael Lyu

IPC分类号： H01L23/31 ,  H01L29/06 ,  H01L29/40 ,  H01L29/34 ,  H01L21/265

CPC分类号： H01L29/408 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/3025 ,  Y10S438/953 ,  Y10S438/958

摘要： A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.

摘要翻译： 公开了具有图案化氮化物钝化层的CMOS集成电路结构，其中图案化氮化物使得其不覆盖一个或多个MOS器件的薄栅极氧化物部分。 当需要防止外部辐射的影响时，PMOS器件的薄栅极氧化物区域被图案化的氮化物钝化层留下。 当需要防止内部产生的“热电子”的影响时，NMOS器件的薄栅极氧化物区域被图案化的氮化物钝化层留下。

公开(公告)号：US5523597A

公开(公告)日：1996-06-04

申请号：US342521

申请日：1994-11-21

申请人： Robert C. Baumann ,  Timothy Z. Hossain

发明人： Robert C. Baumann ,  Timothy Z. Hossain

IPC分类号： H01L21/316 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/31 ,  H01L23/556 ,  H01L27/10 ,  H01L27/108 ,  H01L27/148

CPC分类号： H01L23/556 ,  H01L2924/0002 ,  Y10S257/921 ,  Y10S438/953

摘要： Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.

摘要翻译： 电荷敏感电路元件如易失性存储单元200中的软误差降低是通过使用硼-11来排除在基板206上直接沉积在阵列上的硼硅玻璃230,240中的硼-10或基本上不含硼-10的。 的记忆细胞。 Boron-10在捕获天然存在的宇宙射线中子时表现出很高的裂变可能性释放1.47MeVα粒子。 这种捕获在硼-10中频繁发生，因为其具有高中子俘获截面。 硼11不裂变。

公开(公告)号：US5516731A

公开(公告)日：1996-05-14

申请号：US252723

申请日：1994-06-02

申请人： Shahin Toutounchi ,  Abraham Yee ,  Alexander H. Owens ,  Michael Lyu

发明人： Shahin Toutounchi ,  Abraham Yee ,  Alexander H. Owens ,  Michael Lyu

IPC分类号： H01L21/324 ,  H01L21/326 ,  H01L21/8238 ,  H01L21/477

CPC分类号： H01L21/326 ,  H01L21/324 ,  H01L21/8238 ,  Y10S438/953

摘要： A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.

摘要翻译： 描述了一种用于提高CMOS集成电路的辐射硬度和热电子电阻的技术，其中不期望的氢离子可以通过施加升高的温度和/或电偏压而在覆盖的钝化层中通过任何孔（例如接触孔）排出 到集成电路管芯。 升高的温度和电气偏压有助于加速从模具排出氢气的过程。 消除不需要的氢显着降低了CMOS集成电路中的阈值偏移，提供更大的辐射硬度和热电阻。

公开(公告)号：US5198371A

公开(公告)日：1993-03-30

申请号：US587227

申请日：1990-09-24

申请人： Jianming Li

发明人： Jianming Li

IPC分类号： H01L21/265 ,  H01L21/322 ,  H01L21/762

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/3223 ,  Y10S438/953

摘要： A new-type silicon material is produced by hydrogen ion implantation and subsequent annealing, the annealing being preferably in two steps. The present invention raises surface mobility of a silicon wafer and produces a buried high-resistivity layer beneath a silicon surface layer. The resulting products are particularly useful for the improvement of yield and speed and radiation hardness of very large scale integrated circuits.

摘要翻译： 通过氢离子注入和随后的退火生产新型硅材料，优选退火两步。 本发明提高了硅晶片的表面迁移率，并且在硅表面层下面产生掩埋的高电阻率层。 所得产品对于提高非常大规模集成电路的产量，速度和辐射硬度特别有用。

公开(公告)号：US5021359A

公开(公告)日：1991-06-04

申请号：US416419

申请日：1989-10-03

申请人： William R. Young ,  Anthony L. Rivoli ,  William W. Wiles, Jr.

发明人： William R. Young ,  Anthony L. Rivoli ,  William W. Wiles, Jr.

IPC分类号： H01L21/765 ,  H01L27/092 ,  H01L27/12

CPC分类号： H01L27/092 ,  H01L21/765 ,  H01L27/1203 ,  Y10S438/953

摘要： Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.

摘要翻译： 具有垂直隔离沟槽的集成电路通过在沟槽中提供垂直栅极段（优选为掺杂多晶硅）而被辐射硬化，并且在沟槽的底部连接到相同导电类型的区域。 表面器件可以是互补的，并且垂直栅极也可以是互补掺杂的。 对于单晶晶片以及SOI，描述了制造方法。

公开(公告)号：US4849366A

公开(公告)日：1989-07-18

申请号：US144272

申请日：1988-01-15

申请人： Je-Jung Hsu ,  Hsing-Hai Chen

发明人： Je-Jung Hsu ,  Hsing-Hai Chen

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L21/765 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/765 ,  Y10S438/953

摘要： The invention relates to a radiation hardened (R-H) bulk complementary metal oxide semiconductor (CMOS) isolation structure and a process for its formation. The isolation structure may be automatically generated from the original thin oxide layer of any commercial product by computer aided design and basically comprises a grounded MOS gate surrounding the active areas. The grounded MOS gate replaces the conventional LOCOS field oxide and consists of novel oxide-silicon nitride-oxynitride gate insulator and a CVD polysilicon film. The radiation resistance of this gated isolated structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuit (.ltoreq.2 .mu.m design rule).