Critical dimension uniformity
    41.
    发明授权

    公开(公告)号:US11055464B2

    公开(公告)日:2021-07-06

    申请号:US16175687

    申请日:2018-10-30

    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

    Method for self-adaptively optimizing parameters of a main circuit in a BBMC based on a current rating

    公开(公告)号:US10915692B2

    公开(公告)日:2021-02-09

    申请号:US16909825

    申请日:2020-06-23

    Abstract: Taking parameters of a main circuit in a BBMC as optimization objects, and a total harmonic distortion of an output voltage of the BBMC, a deviation between an actual output current and a corresponding rated output current as optimization objectives, a mathematical model between optimization objects and optimization objectives is established. A multi-objective optimization satisfaction function and a multi-objective optimization fitness function are established by selecting a current rating as a rated output current of the BBMC. An adaptive wolf pack optimization algorithm is adopted to obtain a set of optimal parameters of the main circuit. The rated output current is changed to obtain n sets of optimal parameters, and functional relationships between the optimal parameters of the main circuit in the BBMC are obtained using a numerical fitting method. Optimal parameters of the main circuit corresponding to different current ratings are determined according to the functional relationships.

    Spine routing and pin grouping with multiple main spines

    公开(公告)号:US10719653B2

    公开(公告)日:2020-07-21

    申请号:US15654363

    申请日:2017-07-19

    Applicant: Synopsys, Inc.

    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.

    CRITICAL DIMENSION UNIFORMITY
    49.
    发明申请

    公开(公告)号:US20240386176A1

    公开(公告)日:2024-11-21

    申请号:US18786780

    申请日:2024-07-29

    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

    DESIGN METHOD AND SYSTEM FOR DIRECT-CURRENT LOOP IMPEDANCE

    公开(公告)号:US20240362388A1

    公开(公告)日:2024-10-31

    申请号:US18560100

    申请日:2021-09-13

    CPC classification number: G06F30/373 G06F2111/06

    Abstract: A method and a system for determining a direct current (DC) loop impedance are provided. The method includes: establishing an impedance model for a DC loop of a high-voltage direct current (HVDC) system; scanning parameters in the HVDC system based on the impedance model, to obtain a feasible region of each of the parameters; substituting, for each of the parameters, the parameter in the feasible region into a DC loop impedance equation, to obtain an impedance corresponding to the parameter, the DC loop impedance equation being obtained by transforming the impedance model; and comparing, for each of the parameters, the impedance corresponding to the parameter with a target impedance value, and determining the impedance that meets the target impedance value and the parameter corresponding to the impedance as an optimal impedance and an optimal parameter of the DC loop.

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