公开(公告)号：US20210326507A1

公开(公告)日：2021-10-21

申请号：US17358407

申请日：2021-06-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chi-Ta Lu ,  Chi-Ming Tsai

IPC分类号： G06F30/39

摘要： A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

公开(公告)号：US20210225723A1

公开(公告)日：2021-07-22

申请号：US17201856

申请日：2021-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20180284595A1

公开(公告)日：2018-10-04

申请号：US15475137

申请日：2017-03-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Hung Lai ,  Chih-Chung Huang ,  Chih-Chiang Tu ,  Chung-Hung Lin ,  Chi-Ming Tsai ,  Ming-Ho Tsai

IPC分类号： G03F1/22 ,  G03F7/20

CPC分类号： G03F1/22 ,  G03F1/36 ,  G03F7/7015 ,  G03F7/70441

摘要： A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 μm2 to 60000 μm2. The second pattern has an area of 0.16 μm2 to 60000 μm2. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.

公开(公告)号：US20240178091A1

公开(公告)日：2024-05-30

申请号：US18435362

申请日：2024-02-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/3157 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/16 ,  H01L23/5226 ,  H01L23/528

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US11935804B2

公开(公告)日：2024-03-19

申请号：US18297927

申请日：2023-04-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/3157 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/16 ,  H01L23/5226 ,  H01L23/528

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20230367943A1

公开(公告)日：2023-11-16

申请号：US18360445

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chi-Ta Lu ,  Chi-Ming Tsai

IPC分类号： G06F30/39

CPC分类号： G06F30/39 ,  G06F2111/06

摘要： A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

公开(公告)号：US09630295B2

公开(公告)日：2017-04-25

申请号：US13944353

申请日：2013-07-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： He-Hui Peng ,  Fu-Ming Huang ,  Shich-Chang Suen ,  Han-Hsin Kuo ,  Chi-Ming Tsai ,  Liang-Guang Chen

IPC分类号： B24B53/017 ,  H01L21/304 ,  B08B3/02

CPC分类号： B24B53/017 ,  B08B3/02 ,  H01L21/304

摘要： Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided.

公开(公告)号：US20230245939A1

公开(公告)日：2023-08-03

申请号：US18297927

申请日：2023-04-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

CPC分类号： H01L23/3157 ,  H01L23/16 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/528

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US10861814B2

公开(公告)日：2020-12-08

申请号：US15965981

申请日：2018-04-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzung-Hui Lee ,  Chen-Hua Yu ,  Chi-Ming Tsai ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/683

摘要： Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a bump structure, a polymer layer and a metal layer. The bump structure includes a metal pad and a bump electrically connected to the metal pad. The polymer layer extends laterally from a sidewall of the bump. The metal layer is over the bump structure and in physical contact with a side surface of the metal pad.

公开(公告)号：US11763057B2

公开(公告)日：2023-09-19

申请号：US17358407

申请日：2021-06-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chi-Ta Lu ,  Chi-Ming Tsai

IPC分类号： G06F30/39 ,  G06F111/06

CPC分类号： G06F30/39 ,  G06F2111/06

摘要： A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.