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公开(公告)号:US20240385507A1
公开(公告)日:2024-11-21
申请号:US18787490
申请日:2024-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US12124163B2
公开(公告)日:2024-10-22
申请号:US18359954
申请日:2023-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US11860530B2
公开(公告)日:2024-01-02
申请号:US17809979
申请日:2022-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US20210326507A1
公开(公告)日:2021-10-21
申请号:US17358407
申请日:2021-06-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chi-Ming Tsai
IPC: G06F30/39
Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
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公开(公告)号:US20240386176A1
公开(公告)日:2024-11-21
申请号:US18786780
申请日:2024-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chi-Ming Tsai
IPC: G06F30/39 , G06F111/06
Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
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公开(公告)号:US20230367943A1
公开(公告)日:2023-11-16
申请号:US18360445
申请日:2023-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chi-Ming Tsai
IPC: G06F30/39
CPC classification number: G06F30/39 , G06F2111/06
Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
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公开(公告)号:US20230367197A1
公开(公告)日:2023-11-16
申请号:US18359954
申请日:2023-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US20220350235A1
公开(公告)日:2022-11-03
申请号:US17809979
申请日:2022-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US20220066312A1
公开(公告)日:2022-03-03
申请号:US17007920
申请日:2020-08-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US12254258B2
公开(公告)日:2025-03-18
申请号:US18360445
申请日:2023-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chi-Ming Tsai
IPC: G06F30/39 , G06F111/06
Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
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