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公开(公告)号：US11184011B2
公开(公告)日：2021-11-23
申请号：US16888627
申请日：2020-05-29
摘要： Systems and methods are disclosed for an audio processor that includes a clock detection circuit and a clock bypass circuit. According to various embodiments, the clock detection circuit can check and indicate the status of a main clock and upon detection of a loss of the main clock, the clock bypass circuit can switch the source of the main clock to an alternate source such as an on chip oscillator allowing the system to gracefully recover from the clock loss event.
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公开(公告)号：US20210356985A1
公开(公告)日：2021-11-18
申请号：US16620547
申请日：2019-04-16
发明人： Xiangye WEI
摘要： A time synchronization device adapted for an electronic apparatus, an electronic apparatus, a time synchronization system and a time synchronization method. The time synchronization device includes: a signal generating circuit and a time adjusting circuit. The signal generating circuit includes: a control circuit, configured to generate a frequency control word; and a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal. The time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.
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公开(公告)号：US20210344529A1
公开(公告)日：2021-11-04
申请号：US17323271
申请日：2021-05-18
申请人： Rambus Inc.
摘要： A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
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公开(公告)号：US20210328758A1
公开(公告)日：2021-10-21
申请号：US16849036
申请日：2020-04-15
发明人： Vivek Sarda
摘要： A line card in a network box receives a SyncE clock signal and an input SYNC signal. A phase-lock loop (PLL) in the line card receives the SyncE clock signal as a reference clock signal and generates an output SyncE clock signal. The line card regenerates a SYSCLK signal using a digitally controlled oscillator that receives a timing signal from the SyncE PLL and receives a control signal from control logic on the line card. The frequency and phase information contained in the SYNC signal is utilized to control the DCO. The SYSCLK signal is divided to generate an output SYNC signal. The control logic uses the time difference between the input SYNC signal and a SYNC feedback signal to control the DCO to provide a zero delay SYNC output signal. The output SYNC signal and the SYSCLK signal control a time of day counter in the line card.
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公开(公告)号：US20210314135A1
公开(公告)日：2021-10-07
申请号：US17215428
申请日：2021-03-29
摘要： A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.
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公开(公告)号：US11115005B2
公开(公告)日：2021-09-07
申请号：US16835778
申请日：2020-03-31
发明人： Xiong Liu , Chih-Wei Yao
摘要： A ring voltage controlled oscillator (VCO) circuit is herein provided. According to one embodiment, a ring VCO circuit includes a plurality of stages connected in series, wherein each stage includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter connected in parallel with the third and fourth inverters and the second inverter connected in parallel with the third and fourth inverters, and a first biasing resistor connected to a first node and coupled to an input of the first inverter. The first biasing resistor includes a first switch configured to set the first biasing resistor to about zero voltage.
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公开(公告)号：US11101974B2
公开(公告)日：2021-08-24
申请号：US16118404
申请日：2018-08-30
发明人： Hiroyuki Kobayashi
摘要： A clock and data recovery device of a memory system receives a multiplexed data signal obtained by multiplexing a plurality of data units, each of which is to be transmitted to one of a plurality of memories for storage therein, in an area corresponding to each memory in an amplitude direction and a time direction. The clock and data recovery device includes a clock generation circuit configured to generate a clock, and a data recovery circuit configured to execute phase synchronization with respect to a synchronization signal included in the multiplexed data signal using the generated clock and to recover one of the data units from the area corresponding to one of the memories, from the multiplexed data signal.
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公开(公告)号：US11095338B2
公开(公告)日：2021-08-17
申请号：US16261806
申请日：2019-01-30
IPC分类号： H04B1/717 , H04L7/00 , H04B1/16 , H04B1/3827 , H04L25/49 , H04L27/22 , H04L1/00 , H04L27/26 , H04L5/00 , H04L25/00 , H04B1/7183 , H04L7/033 , H04L25/03
摘要： Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.
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公开(公告)号：US11075784B1
公开(公告)日：2021-07-27
申请号：US17014927
申请日：2020-09-08
申请人： Apple Inc.
发明人： Mark T. Dawkins , Yi-An Li , Yen-Ling Huang
摘要： The present disclosure is directed a wideband multiphase transmitter with two-point modulation. A transmitter includes a control circuit configured to receive a source signal having amplitude and phase components. Using the phase component, the control circuit generates a frequency control signal and a phase jump signal. The transmitter further includes a phase conversion circuit configured to generate a first phase-modulated signal using the phase component and the frequency control signal. The phase conversion circuit is also configured to adjust the phase of the first phase-modulated signal using the phase jump signal. The first phase-modulate signal and the amplitude component are provided to an amplifier, which generates a transmit signal based thereon.
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公开(公告)号：US20210218405A1
公开(公告)日：2021-07-15
申请号：US17143431
申请日：2021-01-07
申请人： ARTILUX, INC.
发明人： Shao-Hung Lin
摘要： Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and/or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and a output reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.
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