公开(公告)号：US5010439A

公开(公告)日：1991-04-23

申请号：US364174

申请日：1989-06-12

Applicant: Michele Zisa ,  Sergio Palara

Inventor： Michele Zisa ,  Sergio Palara

IPC: H02H9/04 ,  H03K17/06 ,  H03K17/0814 ,  H03K17/567 ,  H03K17/687 ,  H03K17/695

CPC classification number: H03K17/08142 ,  H03K17/063 ,  H03K17/6877

Abstract: The power device has a power supply terminal, a load terminal connected to earth by means of an inductive load and a control terminal connected to a circuit with inlet for an alternating control signal. Whenever the power device is turned off, a switching element hitches the voltage of the control terminal to that of the load terminal, which is forced to fall by the inductive load. There is provided a discharge circuit of the inductive load, which includes means having a predetermined threshold which are fired when the voltage of the load terminal falls down to said predetermined threshold.

公开(公告)号：US4994730A

公开(公告)日：1991-02-19

申请号：US448498

申请日：1989-12-11

Applicant: Domenico Rossi ,  Ermes Viani ,  Guido Torelli ,  Franco Maloberti ,  Carla Vacchi

Inventor： Domenico Rossi ,  Ermes Viani ,  Guido Torelli ,  Franco Maloberti ,  Carla Vacchi

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/262

Abstract: A current source circuit capable of generating two currents of opposite polarities. In order to generate the two currents, the circuit comprises a current source stage including a current mirror and feeding a first output current and an inverter stage connected to the source stage and generating a second output current with opposite polarity with respect to the first. The inverter stage comprises a current mirror and a variable current source defining a control electrode. In order to eliminate the differences in the amplitude of the output currents, the inverter stage comprises a memory element connected to the control electrode so as to store an electrode controlling signal. Switch elements are furthermore interposed between the first output and the second output so as to short-circuit them during the trimming step so that the two output currents are equal to one another while the memory element memorizes the control signal. This signal remains stored during the normal operation of the circuit.

公开(公告)号：US4989114A

公开(公告)日：1991-01-29

申请号：US497026

申请日：1990-03-22

Applicant: Sandro Storti ,  Bruno Murari ,  Franco Consiglieri

Inventor： Sandro Storti ,  Bruno Murari ,  Franco Consiglieri

IPC: H01L27/06 ,  H01L21/8222 ,  H02H9/04 ,  H02H11/00 ,  H02P7/00

CPC classification number: H02H11/002 ,  H02P7/04 ,  H02H9/047 ,  Y10T307/839

Abstract: The additional voltage drop across a guard diode against supply polarity inversion in an integrated bridge circuit for driving an external load and employing two high-side NPN power switches driven by two PNP transistors, all monolithically integrated using a junction-type isolation technique, is substantially eliminated by connecting the emitters of the two PNP drive transistors directly to the positive rail, i.e. to the anode of the guard diode. Integrated PNP transistors are per se intrinsically protected against polarity inversion and when so connected permit to reduce the overall voltage drop across the driving bridge circuit. Using a Zener diode as the guard diode and a second Zener diode connected in opposition to the first Zener between the cathode thereof and the negative supply rail an additional spike protection of the circuit's components is implemented.

公开(公告)号：US4987088A

公开(公告)日：1991-01-22

申请号：US381283

申请日：1989-07-18

Applicant: Carlo Bergonzoni ,  Tiziana Cavioni ,  Giuseppe P. Crisenza

Inventor： Carlo Bergonzoni ,  Tiziana Cavioni ,  Giuseppe P. Crisenza

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/105

CPC classification number: H01L21/823807 ,  H01L27/105

Abstract: A process for fabricating CMOS integrated devices includes forming an n-type deep well diffusion region in a surface of a p-type monocrystalline silicon substrate. Transistor devices having a p-type channel region are formed within the deep well diffusion regions, and transistor devices having an n-type channel region are formed external the deep well diffusion regions. The improvement of the present invention includes the step of performing an unmasked ion implantation of boron over the entire surface of the monocrystalline silicon substrate after having formed the deep well diffusion regions in order to effect simultaneously a partial compensation of a superficial doping level of the deep well diffusion region and an enrichment of a superficial doping level of the monocrystalline silicon substrate external the deep well diffusion region.

公开(公告)号：US4972130A

公开(公告)日：1990-11-20

申请号：US435889

申请日：1989-11-14

Applicant: Domenico Rossi ,  Andrea Cuomo ,  Giovanni Pietrobon

Inventor： Domenico Rossi ,  Andrea Cuomo ,  Giovanni Pietrobon

IPC: H02P8/12 ,  H02P7/00 ,  H03K17/687 ,  H03K17/693 ,  H03K17/695

CPC classification number: H03K17/6871 ,  H02P7/04 ,  H03K17/693

Abstract: A multipurpose integrated circuit for driving in a switching mode an externally connected load or loads permits implementation of any appropriate supply scheme of the external load or loads through six output terminals thereof and is therefore useful in a large number of applications. The integrated circuit uses six integrated power switching devices provided with respective recirculation diodes and a single externally connected sensing resistor for generating, by means of a customary PWM control loop, a control signal by which means of a logic circuit configurable by progrmaming permits the generation of driving signals as a function of the control signal for all six integrated power switches in accordance with a configuration of the driving signals which conforms with the particular scheme of connection of the load or loads selected among the different bridge type and unipolar-motor type schemes which may be selected by programming. A multiplexer is used for selecting among bridge type driving signals and unipolar-motor type driving modes and a ROM provided with two input registers for selecting the specific driving scheme and for regulation, respectively.

公开(公告)号：US4968639A

公开(公告)日：1990-11-06

申请号：US284272

申请日：1988-12-14

Applicant: Carlo Bergonzoni

Inventor： Carlo Bergonzoni

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/78 ,  H01L27/0928

Abstract: A process for manufacturing CMOS integrated devices with gate lengths of less than one micron and high supply voltage is described. In order to improve the resistance of CMOS devices to breakdown and punch-through phenomena without cost increases with respect to conventional CMOS processes and limiting as much as possible the introduction of resistances in series to the transistors, less doped source and drain regions being provided in only one of the two MOS transistors, e.g. in the N-channel transistor, to increase the breakdown voltage, an oppositely doped region, e.g. with P-type doping, being provided around the source and drain regions of this first transistor to protect this first transistor against punch-through, and doped wells being provided around the source and drain regions of the complementary transistor, which is e.g. a P-channel transistor; the doped wells being oppositely doped with respect to the source and drain regions but having a lower doping level than the region of the body of semiconductor material which accommodates the complementary transistor, in order to increase the breakdown voltage of the P-channel complementary transistor.

公开(公告)号：US4956569A

公开(公告)日：1990-09-11

申请号：US373203

申请日：1989-06-30

Applicant: Marco Olivo ,  Luigi Pascucci ,  Carlo Riva ,  Paolo Rosini ,  Corrado Villa

Inventor： Marco Olivo ,  Luigi Pascucci ,  Carlo Riva ,  Paolo Rosini ,  Corrado Villa

IPC: H01L21/8238 ,  H01L27/092 ,  H03K3/356 ,  H03K3/3565 ,  H03K19/003

CPC classification number: H03K19/00315 ,  H03K3/356104 ,  H03K3/3565

Abstract: A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.

公开(公告)号：US4952934A

公开(公告)日：1990-08-28

申请号：US465703

申请日：1990-01-16

Applicant: Antonio Chiriatti

Inventor： Antonio Chiriatti

IPC: G05B15/02 ,  G05B19/045 ,  G06J1/00

CPC classification number: G05B19/045 ,  G05B15/02 ,  G06J1/00 ,  Y10T307/826

Abstract: A programmable logic and analogic integrated device comprises a programmable logic section capable of constituting by programming a state machine which beside producing outpout logic signals in function of input logic signals may drive a digital-analog converter (DAC), the analog signal generated by which is managed as well as other analog signals which may be respectively fed to a number of analog input pins of the integrated device by the said programmable state machine by means of a plurality of integrated analog switches which also permit the output of the analog signal generated by the DAC through a buffered analog output pin of the device. An integrated comparator (zero-crossing detector) provides a comparison between two distinct external analog signals or between an external analog signal and the analog signal generated by the DAC for producing an output logic signal which may be fed to an input of the state machine for implementing a certain interaction function.The device is useful for a wide range of applications in lieu of a microprocessor based system.

Abstract translation: 可编程逻辑和模拟集成装置包括能够通过编程状态机构成的可编程逻辑部分，其旁边产生输入逻辑信号功能的输出逻辑信号可以驱动数模转换器（DAC），由其产生的模拟信号 管理以及可以通过多个集成模拟开关分别馈送到所述可编程状态机的集成设备的多个模拟输入引脚的其他模拟信号，所述多个集成模拟开关还允许输出由 DAC通过缓冲模拟输出引脚的器件。 集成比较器（过零检测器）提供两个不同的外部模拟信号之间或外部模拟信号与DAC产生的模拟信号之间的比较，用于产生输出逻辑信号，该输出逻辑信号可被馈送到状态机的输入端 实现一定的互动功能。 该设备对于广泛的应用代替基于微处理器的系统是有用的。

公开(公告)号：US4922402A

公开(公告)日：1990-05-01

申请号：US372493

申请日：1989-06-28

Applicant: Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

Inventor： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073

Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

公开(公告)号：US4916378A

公开(公告)日：1990-04-10

申请号：US380220

申请日：1989-07-14

Applicant: Fabio Marchio' ,  Marco Morelli ,  Francesco Tricoli

Inventor： Fabio Marchio' ,  Marco Morelli ,  Francesco Tricoli

IPC: H01L27/06 ,  H01L21/8222 ,  H02P8/12 ,  H03K17/0814 ,  H03K17/16 ,  H03K17/64

CPC classification number: H03K17/08146

Abstract: A circuit for recirculating the discharge current of an inductive load driven from the high side of the supply at two different recirculation voltages which may be selected for implementing a slow or a fast recirculation of the current advantageously employs a single power element represented by an NPN transistor functionally connected in parallel to the load. During a driving phase of the load a slow recirculation of the discharge current is implemented by delivering to the base of the recirculation NPN transistor a current sufficient to keep it saturated. upon switching off the load, when a fast recirculation of the dischage current through the recirculation NPN transistor is desired, delivery of the saturating current to the base of the recirculation transistor is interrupted and the transistor remains conducting having a diode and a zener diode in opposition thereto connected in series between ground and the base of the recirculation NPN transistor for permitting the recirculation at a voltage substantially equal to the sum of the voltage drop through the first diode, the zener voltage and the base-emitter voltage of the recirculation NPN transistor.