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公开(公告)号：US20210200468A1
公开(公告)日：2021-07-01
申请号：US16730092
申请日：2019-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Jing Wang , James R. Magro , Kedarnath Balakrishnan
IPC: G06F3/06
Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.
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公开(公告)号：US20210191435A1
公开(公告)日：2021-06-24
申请号：US16723920
申请日：2019-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Sonu Arora , Michael Arn Nix , Moises E. Robinson , Xiaojie He
IPC: G05F1/46 , G05B19/042
Abstract: A technique for adjusting a power supply for a device is provided. The technique includes detecting a low-power trigger for a device; switching a power supply for the device from a high-power power supply to a low-power power supply; detecting a high-power trigger for a device; and switching a power supply for the device from the low-power power supply to the high-power power supply, wherein the high-power power supply consumes a larger amount of power than the low-power power supply, and wherein the high-power power supply provides a greater amount of noise reducing and a greater tolerance to temperature differences than the low-power power supply.
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公开(公告)号：US20210185333A1
公开(公告)日：2021-06-17
申请号：US17185497
申请日：2021-02-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael L. Schmit , Ashish Farmer , Radhakrishna Giduthuri
IPC: H04N19/43 , H04N19/436
Abstract: A host processor, such as a central processing unit (CPU), programmed to execute a software driver that causes the host processor to generate a motion compensation command for a plurality of cores of a massively parallel processor, such as a graphics processing unit (GPU), to provide motion compensation for encoded video. The motion compensation command for the plurality of cores of the massively parallel processor contains executable instructions for processing a plurality of motion vectors grouped by a plurality of prediction modes from a re-ordered motion vector buffer by the plurality of cores of the massively parallel processor.
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公开(公告)号：US20210183668A1
公开(公告)日：2021-06-17
申请号：US16715459
申请日：2019-12-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Travis Oneal Cagle , Sheldon S. Grooms
Abstract: Systems, apparatuses, and methods for efficiently performing active thermal control during device testing are disclosed. A device testing system includes a device under test, a thermal structure on top of the device under test, and a controller configured to determine when to apply and remove thermal energy to the device under test through the thermal structure. The thermal structure includes a thermal transfer block that transfers thermal energy to and from the device under test below the thermal transfer block. The thermal structure also includes a coolant block above the thermal transfer block that removes thermal energy from the thermal transfer block. There is no heating element between the coolant block and the thermal transfer block. Rather, the thermal structure includes a heating element in a wall of the thermal transfer block. Therefore, an unobstructed thermal path exists from the device under test to the coolant block.
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公开(公告)号：US20210182582A1
公开(公告)日：2021-06-17
申请号：US16722499
申请日：2019-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Chang-Che Tsai , Chih-Wei Li , Po-Min Wang , Yang Wang
Abstract: A processing device comprises a memory configured to store data and a processor. The processor is configured to control an exposure timing of a rolling shutter image sensor and an IR illumination timing of an object, by an IR light emitter, by switching between a first operation mode and a second operation mode. In the first operation mode, a sequence of video frames, each having a plurality of pixel lines, comprises a frame in which each pixel line is exposed to IR light emitted by the IR light emitter; a frame which is partially exposed to the IR light and a frame in which no pixel line is exposed to the IR light. In the second operation mode, alternating video frames of the sequence comprise one of a frame in which each pixel line is exposed to the IR light and a frame in which no pixel line is exposed to the IR light.
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Patent Agency Ranking
公开(公告)号：US20210182262A1
公开(公告)日：2021-06-17
申请号：US16717027
申请日：2019-12-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Nuwan Jayasena
Abstract: A method and apparatus perform a first hash operation on a first key wherein the first hash operation is biased to map the first key and associated value to a set of frequently-accessed buckets in a hash table. An entry for the first key and associated value is stored in the set of frequently-accessed buckets. A second hash operation is performed on a second key wherein the second hash operation is biased to map the second key and associated value to a set of less frequently-accessed buckets in the hash table. An entry for the second key and associated value is stored in the set of less frequently-accessed buckets. The method and apparatus perform a hash table look up of the requested key in the set of frequently-accessed buckets, if the requested key is not found, then a hash table lookup is performed in the set of less frequently-accessed buckets.
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公开(公告)号：US20210182213A1
公开(公告)日：2021-06-17
申请号：US16716165
申请日：2019-12-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Jieming Yin , Yasuko Eckert , Subhash Sethumurugan
IPC: G06F12/122
Abstract: Systems, apparatuses, and methods for implementing cache line re-reference interval prediction using a physical page address are disclosed. When a cache line is accessed, a controller retrieves a re-reference interval counter value associated with the line. If the counter is less than a first threshold, then the address of the cache line is stored in a small re-use page buffer. If the counter is greater than a second threshold, then the address is stored in a large re-use page buffer. When a new cache line is inserted in the cache, if its address is stored in the small re-use page buffer, then the controller assigns a high priority to the line to cause it to remain in the cache to be re-used. If a match is found in the large re-use page buffer, then the controller assigns a low priority to the line to bias it towards eviction.
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公开(公告)号：US20210182135A1
公开(公告)日：2021-06-17
申请号：US16718168
申请日：2019-12-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Sudhanva Gurumurthi , Vilas K. Sridharan
Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.
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公开(公告)号：US20210182072A1
公开(公告)日：2021-06-17
申请号：US16713432
申请日：2019-12-13
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Alexander Fuad ASHKAR , Manu RASTOGI , Harry J. WISE
Abstract: A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.
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公开(公告)号：US20210173702A1
公开(公告)日：2021-06-10
申请号：US16709527
申请日：2019-12-10
Applicant: Advanced Micro Devices, Inc.
Inventor： Alok Garg , Scott Andrew McLelland , Marius Evers , Matthew T. Sobel
IPC: G06F9/48
Abstract: Systems, apparatuses, and methods for implementing scheduler queue assignment burst mode are disclosed. A scheduler queue assignment unit receives a dispatch packet with a plurality of operations from a decode unit in each clock cycle. The scheduler queue assignment unit determines if the number of operations in the dispatch packet for any class of operations is greater than a corresponding threshold for dispatching to the scheduler queues in a single cycle. If the number of operations for a given class is greater than the corresponding threshold, and if a burst mode counter is less than a burst mode window threshold, the scheduler queue assignment unit dispatches the extra number of operations for the given class in a single cycle. By operating in burst mode for a given operation class during a small number of cycles, processor throughput can be increased without starving the processor of other operation classes.
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