公开(公告)号：US06246103B1

公开(公告)日：2001-06-12

申请号：US09427136

申请日：1999-10-25

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2900

CPC classification number: H01L29/7311

Abstract: A MOSBJT (Metal Oxide Semiconductor Bipolar Junction Transistor) is formed to have both the higher current drive capability of the BJT and the smaller device area of the scaled down MOSFET. The MOSBJT includes a collector region and an emitter region comprised of a semiconductor material with a first type of dopant. A base region is disposed between the collector region and the emitter region, and the base region is comprised of a semiconductor material with a second type of dopant that is opposite of the first type of dopant. Unlike a conventional BJT, a base terminal of the MOSBJT is comprised of a dielectric structure disposed over the base region and comprised of a gate structure disposed over the dielectric structure. Unlike a conventional MOSFET, the dielectric structure of the MOSBJT is relatively thin such that a tunneling current through the dielectric structure results when a turn-on voltage is applied on the gate structure. This tunneling current is a base current of the MOSBJT. Furthermore, unlike a conventional MOSFET, the dielectric structure and the gate structure of the MOSBJT are not disposed over the collector region and the emitter region to prevent tunneling current between the gate structure and the collector and emitter regions.

Abstract translation: 形成MOSBJT（金属氧化物半导体双极结晶体管）以具有BJT的较高电流驱动能力和缩小的MOSFET的较小器件面积。 MOSBJT包括集电极区域和由具有第一类型掺杂剂的半导体材料组成的发射极区域。 基极区域设置在集电极区域和发射极区域之间，并且基极区域由具有与第一类型掺杂剂相反的第二类型掺杂剂的半导体材料构成。 与常规BJT不同，MOSBJT的基极端子由设置在基极区域上的电介质结构构成，并且包括设置在电介质结构上的栅极结构。 与常规MOSFET不同，MOSBJT的电介质结构相对较薄，使得当在栅极结构上施加导通电压时，导致通过电介质结构的隧穿电流。 该隧穿电流是MOSBJT的基极电流。 此外，与传统的MOSFET不同，MOSBJT的电介质结构和栅极结构不设置在集电极区域和发射极区域上，以防止栅极结构与集电极和发射极区域之间的隧穿电流。

公开(公告)号：US06218711B1

公开(公告)日：2001-04-17

申请号：US09253574

申请日：1999-02-19

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L31119

CPC classification number: H01L29/66628 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L29/665

Abstract: A MOSFET with raised source/drains that can readily be silicidated and have shallow source/drain extensions. The invention uses chemical vapor epitaxy to create raised source/drains. The invention provides molecules containing silicon and molecules containing germanium, preferably GeH4, for the chemical vapor epitaxy. Initially, the concentration of GeH4 is between 5 to 10% of the concentration of molecules containing silicon. During the chemical vapor epitaxy, the concentration of GeH4 is reduced to zero. The raised source/drains and the gate are subjected to silicidation. The higher concentrations of GeH4allow more selective epitaxy to silicon, thus preventing deposition on the polysilicon gate, nitride spacers and isolation trenches. It also allows for the use of lower epitaxy temperatures reducing movements of dopants in the source/drain extension. The slow reduction in concentration of GeH4 allows for the epitaxy temperature to be kept low. The reduced germanium concentration near the end of the epitaxy allows better silicidation of the raised source/drain.

Abstract translation: 具有升高的源极/漏极的MOSFET，其可以容易地被硅化并具有浅的源极/漏极延伸。 本发明使用化学气相外延来产生升高的源/排水。 本发明提供含有硅的分子和含锗的分子，优选为GeH 4，用于化学气相外延。 最初，GeH 4的浓度为含硅分子浓度的5至10％。 在化学气相外延期间，GeH4的浓度降低到零。 升高的源极/漏极和栅极经受硅化。 较高浓度的GeH4allow对硅进行更多的选择性外延，从而防止沉积在多晶硅栅极，氮化物间隔物和隔离沟槽上。 它还允许使用较低的外延温度降低源极/漏极延伸中的掺杂剂的移动。 GeH4浓度的缓慢降低允许外延温度保持较低。 在外延结束附近的锗浓度降低，可以使升高的源极/漏极更好的硅化。

公开(公告)号：US06214654B1

公开(公告)日：2001-04-10

申请号：US09238358

申请日：1999-01-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21338

CPC classification number: H01L29/66537 ,  H01L21/26506 ,  H01L29/105 ,  H01L29/66545

Abstract: A method for making a ULSI MOSFET chip includes forming a sacrificial gate on a substrate along with activated source and drain regions, but without initially establishing a doped channel region. The polysilicon portion of the sacrificial gate is then removed and a neutral ion species such as Silicon or Germanium is implanted between the source and drain regions in the region that is to become the doped channel region. A dopant substance is next implanted into the channel region, which is then exposed to ultra-rapid thermal annealing to cause the dopant to form a box-like, super-steep retrograded channel profile. The gate is then re-formed over the now activated doped channel region.

Abstract translation: 制造ULSI MOSFET芯片的方法包括在激活的源极和漏极区域上在衬底上形成牺牲栅极，但是没有初始建立掺杂沟道区域。 然后去除牺牲栅极的多晶硅部分，并且在将要成为掺杂沟道区域的区域中的源极和漏极区域之间注入中性离子物质，例如硅或锗。 接着将掺杂剂物质注入到沟道区域中，然后暴露于超快速热退火以使掺杂剂形成盒状，超陡峭的退化的沟道轮廓。 然后在现在激活的掺杂沟道区上重新形成栅极。

公开(公告)号：US06187642B1

公开(公告)日：2001-02-13

申请号：US09334119

申请日：1999-06-15

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L21336

CPC classification number: H01L29/7834 ,  B01J2219/00315 ,  B01J2219/00317 ,  B01J2219/00527 ,  B01J2219/00585 ,  B01J2219/0059 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01J2219/00686 ,  B01J2219/00689 ,  B01J2219/00713 ,  B01J2219/0072 ,  B01J2219/00722 ,  B01J2219/00725 ,  B01J2219/00731 ,  B82Y5/00 ,  B82Y10/00 ,  C07B2200/11 ,  C07H21/00 ,  C40B40/06 ,  C40B40/10 ,  C40B40/12 ,  C40B60/14 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C19/00 ,  H01L25/50 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate. The inventive method provides thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The inventive semiconductor devices provide for very shallow source drain extensions which results in a reduced short channel effect.

Abstract translation: 本发明的方法提供了改进的半导体器件，例如在衬底上具有升高的源极/漏极延伸的MOSFET，其中隔离沟槽蚀刻到衬底的表面中。 本发明的方法在栅极和栅极氧化物的一侧提供薄的第一介电间隔物，并且从栅极的顶部延伸到衬底的表面。 引出的源极/漏极延伸部被放置在从第一电介质间隔物延伸到隔离沟槽的衬底的表面上。 更厚的第二电介质间隔物被放置成与第一电介质间隔物相邻并且从第一介电间隔物的顶部延伸到升高的源极/漏极延伸部分。 升高的源极/漏极区域放置在凸起的源极/漏极延伸部上，并且从隔离沟槽延伸到第二电介质间隔物。 本发明的半导体器件提供非常浅的源极漏极延伸，这导致短沟道效应的降低。

公开(公告)号：US06180476B2

公开(公告)日：2001-01-30

申请号：US09187630

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions which utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The shallow amorphous region helps to reduce ion implant channeling effects, and the deep amorphous region helps to getter point defects generated during dopant implants. The process can be utilized for P-channel or N-channel metal field effects semiconductor transistors (MOSFETs).

Abstract translation: 利用双非晶化技术制造具有超浅源极/漏极结的集成电路的方法。 该技术产生了300nm厚的浅非晶区和深非晶区。 浅非晶区域在衬底的顶表面之下10-15nm之间，深非晶区域在衬底顶表面之下的150-200nm之间。 浅非晶区域有助于减少离子注入沟道效应，深非晶区域有助于在掺杂剂注入期间产生的吸气点缺陷。 该过程可用于P沟道或N沟道金属场效应半导体晶体管（MOSFET）。

公开(公告)号：US6127216A

公开(公告)日：2000-10-03

申请号：US187881

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/8234

CPC classification number: H01L21/82345

Abstract: An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs utilize gate structures with heavily doped polysilicon material or heavily doped polysilicon/germanium material. The polysilicon and polysilicon/germanium materials are manufactured by utilizing amorphouse semiconductor layers. Excimer laser annealing is utilized to activate the dopants and to provide a box-like dopant profile.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET利用具有重掺杂多晶硅材料或重掺杂多晶硅/锗材料的栅极结构。 多晶硅和多晶硅/锗材料通过利用顶层半导体层制造。 使用准分子激光退火来激活掺杂剂并提供盒状掺杂物分布。

公开(公告)号：US5953615A

公开(公告)日：1999-09-14

申请号：US238359

申请日：1999-01-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/336

CPC classification number: H01L29/66598 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/268 ,  H01L29/6659 ,  H01L21/26513

Abstract: The inventive method provides MOSFET's with deep source/drain junctions and shallow source/drain extensions. The invention provides on a semiconductor wafer a gate stack with side spacers. The side spacers are etched so that a known thickness of the side spacers is left. An ion beam is used to implant Si.sup.+ or Ge.sup.+ or Xe.sup.+ to amorphize the silicon region, creating an amorphous region with two different depths. A high dose ion beam is then used to implant a dopant. An oxide layer is then deposited as a barrier layer, and then a metal layer is deposited to improve laser energy absorption. Laser annealing is used to melt the amorphous silicon region which causes the dopant to diffuse into the amorphous silicon region creating deep source/drain junctions and shallow source/drain extensions. Conventional techniques are then used to complete the transistor, which includes silicidation of the source/drain junctions. The deep source/drain junctions allow for an easier silicidation. The shallow source/drain extensions help to prevent punch through.

Abstract translation: 本发明的方法提供具有深源极/漏极结和浅源极/漏极延伸的MOSFET。 本发明在半导体晶片上提供具有侧间隔物的栅叠层。 蚀刻侧面间隔物，使得留下已知厚度的侧面间隔物。 使用离子束注入Si +或Ge +或Xe +以使硅区域非晶化，产生具有两个不同深度的非晶区域。 然后使用高剂量离子束来注入掺杂剂。 然后沉积氧化物层作为阻挡层，然后沉积金属层以提高激光能量吸收。 使用激光退火来熔化非晶硅区域，这导致掺杂剂扩散到非晶硅区域，产生深的源极/漏极结和浅的源极/漏极延伸。 然后使用常规技术来完成晶体管，其包括源极/漏极结的硅化。 深源/漏极接点允许更容易的硅化。 浅源/漏扩展有助于防止穿透。