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    FinFET device with multiple fin structures
    1.
    发明授权
    FinFET device with multiple fin structures 有权
    FinFET器件具有多个鳍结构

    公开(公告)号：US07679134B1

    公开(公告)日：2010-03-16

    申请号：US10754515

    申请日：2004-01-12

    Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

    Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

    IPC: H01L29/94

    CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L29/66795

    Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

    Abstract translation: 半导体器件包括一组翅片结构。 翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。 半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

    Semiconductor device having a thin fin and raised source/drain areas
    3.
    发明授权
    Semiconductor device having a thin fin and raised source/drain areas 有权
    半导体器件具有薄的鳍片和升高的源极/漏极区域

    公开(公告)号：US06911697B1

    公开(公告)日：2005-06-28

    申请号：US10632965

    申请日：2003-08-04

    Applicant: Haihong Wang ,  Judy Xilin An ,  Bin Yu

    Inventor： Haihong Wang ,  Judy Xilin An ,  Bin Yu

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618

    Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin, source and drain regions and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The source region is formed on the insulating layer adjacent a first side of the fin and the drain region is formed on the second side of the fin opposite the first side. The source and drain regions have a greater thickness than the fin in the channel region of the semiconductor device.

    Abstract translation: 双栅极半导体器件包括衬底，绝缘层，鳍，源极和漏极区以及栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 源极区域形成在与鳍片的第一侧相邻的绝缘层上，并且漏极区域形成在与第一侧相对的翅片的第二侧上。 源极和漏极区域具有比半导体器件的沟道区域中的鳍片更大的厚度。

    Method for forming a gate in a FinFET device
    4.
    发明授权
    Method for forming a gate in a FinFET device 有权
    在FinFET器件中形成栅极的方法

    公开(公告)号：US06815268B1

    公开(公告)日：2004-11-09

    申请号：US10301732

    申请日：2002-11-22

    Applicant: Bin Yu ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy

    Inventor： Bin Yu ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy

    IPC: H01L2100

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A method of forming a gate in a FinFET device includes forming a fin on an insulating layer, forming source/drain regions and forming a gate oxide on the fin. The method also includes depositing a gate material over the insulating layer and the fin, depositing a barrier layer over the gate material and depositing a bottom anti-reflective coating (BARC) layer over the barrier layer. The method further includes forming a gate mask over the BARC layer, etching the BARC layer, where the etching terminates on the barrier layer, and etching the gate material to form the gate.

    Abstract translation: 在FinFET器件中形成栅极的方法包括在绝缘层上形成鳍片，形成源极/漏极区域并在鳍片上形成栅极氧化物。 该方法还包括在绝缘层和鳍上沉积栅极材料，在栅极材料上沉积阻挡层并在阻挡层上沉积底部抗反射涂层（BARC）层。 该方法还包括在BARC层上形成栅极掩模，蚀刻BARC层，其中蚀刻在阻挡层上终止，并蚀刻栅极材料以形成栅极。

    Double spacer FinFET formation
    7.
    发明授权
    Double spacer FinFET formation 有权
    双间隔FinFET形成

    公开(公告)号：US06709982B1

    公开(公告)日：2004-03-23

    申请号：US10303702

    申请日：2002-11-26

    Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

    Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

    IPC: H01L21311

    CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L29/66795

    Abstract: A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.

    Abstract translation: 一种在半导体器件中形成一组结构的方法包括在基底上形成导电层，其中导电层包括导电材料，并在导电层上形成氧化物层。 该方法还包括蚀刻氧化物层中的至少一个开口，用导电材料填充至少一个开口，蚀刻导电材料以在至少一个开口的侧壁上形成间隔物，并且去除氧化物层和一部分 导电层形成一组结构。

    Method and apparatus for making MOSFETs with elevated source/drain extensions
    8.
    发明授权
    Method and apparatus for making MOSFETs with elevated source/drain extensions 有权
    用于制造具有升高的源极/漏极延伸的MOSFET的方法和装置

    公开(公告)号：US06445042B1

    公开(公告)日：2002-09-03

    申请号：US09687992

    申请日：2000-10-13

    Applicant: Bin Yu ,  Judy Xilin An

    Inventor： Bin Yu ,  Judy Xilin An

    IPC: H01L2976

    CPC classification number: H01L29/6659 ,  G01N21/9501 ,  G01R31/307 ,  G01R31/311 ,  H01J37/21 ,  H01J2237/2817 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S977/869 ,  Y10S977/881 ,  Y10S977/901 ,  Y10S977/954

    Abstract: An improved semiconductor device, such as a MOSFET with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate . The device has thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The semiconductor device has very shallow source drain extensions which result in a reduced short channel effect.

    Abstract translation: 改进的半导体器件，例如在衬底上具有升高的源极/漏极延伸的MOSFET，其具有蚀刻到衬底的表面中的隔离沟槽。 该器件在栅极和栅极氧化物一侧具有薄的第一介电间隔物，并从栅极的顶部延伸到衬底的表面。 引出的源极/漏极延伸部被放置在从第一电介质间隔物延伸到隔离沟槽的衬底的表面上。 更厚的第二电介质间隔物被放置成与第一电介质间隔物相邻并且从第一介电间隔物的顶部延伸到升高的源极/漏极延伸部分。 升高的源极/漏极区域放置在凸起的源极/漏极延伸部上，并且从隔离沟槽延伸到第二电介质间隔物。 半导体器件具有非常浅的源极漏极延伸，导致短沟道效应降低。

    MOS transistor with minimal overlap between gate and source/drain extensions
    9.
    发明授权
    MOS transistor with minimal overlap between gate and source/drain extensions 有权
    MOS晶体管在栅极和源极/漏极延伸之间具有最小的重叠

    公开(公告)号：US06265256B1

    公开(公告)日：2001-07-24

    申请号：US09156238

    申请日：1998-09-17

    Applicant: Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

    Inventor： Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

    IPC: H01L218238

    CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/823468 ,  H01L29/6659

    Abstract: A method for making a ULSI MOSFET includes establishing a gate void in a field oxide layer above a silicon substrate, after source and drain regions with associated source and drain extensions have been established in the substrate. A gate electrode is deposited in the void and gate spacers are likewise deposited in the void on the sides of the gate electrode, such that the gate electrode is spaced from the walls of the void. The spacers, not the gate electrode, are located above the source/drain extensions, such that fringe coupling between the gate electrode and the source and drain extensions is suppressed.

    Abstract translation: 制造ULSI MOSFET的方法包括：在衬底中建立具有相关源极和漏极延伸部分的源极和漏极区域之后，在硅衬底上的场氧化物层中建立栅极空隙。 栅电极沉积在空隙中，并且栅极间隔物同样沉积在栅电极的侧面上的空隙中，使得栅电极与空隙的壁间隔开。 间隔件而不是栅电极位于源极/漏极延伸部上方，从而抑制栅极电极和源极和漏极延伸部之间的边缘耦合。

    Germanium MOSFET devices and methods for making same
    10.
    发明授权
    Germanium MOSFET devices and methods for making same 有权
    锗MOSFET器件及其制造方法

    公开(公告)号：US08334181B1

    公开(公告)日：2012-12-18

    申请号：US12836378

    申请日：2010-07-14

    Applicant: Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

    Inventor： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

    IPC: H01L29/72

    CPC classification number: H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

    Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

    Abstract translation: 双栅极锗金属氧化物半导体场效应晶体管（MOSFET）包括锗翅片，邻近锗翅片的第一侧形成的第一栅极和与第一侧相对的锗翅片第二侧附近形成的第二栅极 。 三栅极MOSFET包括锗翅片，与锗翅片的第一侧相邻形成的第一栅极，与第一侧相对的锗翅片的第二侧附近形成的第二栅极和形成在锗翅片顶部上的顶栅极 。 全栅极MOSFET包括锗翅片，邻近锗翅片的第一侧形成的第一侧壁栅极结构，邻近锗翅片的第二侧形成的第二侧壁栅极结构，以及形成在锗翅片上和周围的附近的栅极结构 锗鳍

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