公开(公告)号：US4904889A

公开(公告)日：1990-02-27

申请号：US277077

申请日：1988-11-28

Applicant: Davide Chieli

Inventor： Davide Chieli

IPC: H03K17/06 ,  H03K17/567

CPC classification number: H03K17/567 ,  H03K17/063

Abstract: A driving circuit comprising a low-voltage power supply line, a MOS transistor having a gate terminal and a drain terminal connected to a load and a control stage connected to the power supply line and to the gate terminal of the MOS transistor. In order to allow the MOS transistor to be switched on even when the voltage of the power supply line is lower than the threshold voltage of the MOS transistor, the driving circuit comprises a bipolar transistor connected in parallel to the MOS transistor and a voltage multiplier circuit connected between a common terminal of the MOS and bipolar transistors and the control stage. The control stage comprises comparators adapted to initially switch on the bipolar transistor so as to feed the multiplier circuit, which is thus capable of generating a voltage higher than the available supply voltage, and to subsequently switch off the bipolar transistor and switch on the MOS transistor when the voltage generated by the voltage multiplier has reached at least the threshold voltage of the MOS transistor.

公开(公告)号：US4902632A

公开(公告)日：1990-02-20

申请号：US288407

申请日：1988-12-21

Applicant: Carmelo Oliveri ,  Carmelo Magro

Inventor： Carmelo Oliveri ,  Carmelo Magro

IPC: G01R31/28 ,  H01L21/66

CPC classification number: H01L22/00 ,  G01R31/2831 ,  Y10S438/958

Abstract: The method consists of subjecting the semiconductor chips to chemical treatment with a silanizing agent immediately before testing to prevent superficial electrical discharges which can reduce the testing voltage which can be applied.

Abstract translation: 该方法包括在测试之前使用硅烷化剂对半导体芯片进行化学处理，以防止能够降低可施加的测试电压的表面放电。

公开(公告)号：US4899069A

公开(公告)日：1990-02-06

申请号：US285204

申请日：1988-12-16

Applicant: Germano Nicollini

Inventor： Germano Nicollini

IPC: H03H19/00

CPC classification number: H03H19/004

Abstract: An integrated, low-pass filter of the first order made using the switched capacitors technique utilizes advantageously a single switched capacitor and only two switches in contrast to the filters of the prior art which utilize two switched capacitors and four switches. The filter of the invention requires a smaller integration area and moreover exhibits a greater precision of its DC gain.

公开(公告)号：US4882532A

公开(公告)日：1989-11-21

申请号：US254763

申请日：1988-10-07

Applicant: Roberto Gariboldi ,  Alberto Gola

Inventor： Roberto Gariboldi ,  Alberto Gola

IPC: G05F3/16 ,  G05F1/10 ,  G05F1/56 ,  H01H47/22 ,  H02H9/04 ,  H03K17/082 ,  H03K17/16 ,  H03K17/64

CPC classification number: H03K17/0826 ,  H01H47/22 ,  H02H9/047

Abstract: A circuit for limiting the transient overvoltage across a power transistor connected in series with an inductive load between a supply rail and a ground rail of the circuit and operated to switch ON-OFF the inductive load utilizes a comparator circuit for switching-ON again the power transistor in order to discharge the energy stored in the load's inductance. The voltage across the power transistor is sensed by a first voltage divider, while a reference voltage is obtained by a second voltage divider connected between the supply and ground. The circuit is practically insensitive to temperature and to variations of the supply voltage and is easily implemented.

公开(公告)号：US20040173840A1

公开(公告)日：2004-09-09

申请号：US10792308

申请日：2004-03-03

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Paolo Cappelletti

IPC: H01L029/788

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/49 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

公开(公告)号：US06148413A

公开(公告)日：2000-11-14

申请号：US835030

申请日：1997-03-28

Applicant: Luigi Pascucci ,  Marco Fontana

Inventor： Luigi Pascucci ,  Marco Fontana

IPC: G11C5/02 ,  G11C16/28 ,  H02H3/05 ,  G11C29/00

CPC classification number: G11C16/28 ,  G11C5/025

Abstract: Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising at least two memory half-matrices, a bidirectional internal bus for the transmission of data to and from the memory half-matrices, a programming unit for each one of the at least two memory half-matrices, and a data sensing unit. The programming units are adapted to program the at least two memory half-matrices and the data sensing unit and the programming units communicate with the bidirectional internal bus to reroute onto the bus reading data and programming data of the at least two memory half-matrices.

Abstract translation: 编程和读取管理架构，特别是用于测试目的，用于非易失性类型的存储器件，包括至少两个存储器半矩阵，用于向存储器半矩阵传输数据和从存储器半矩阵传输数据的双向内部总线，编程 所述至少两个存储器半矩阵中的每一个的单元，以及数据感测单元。 所述编程单元适于对所述至少两个存储器半矩阵进行编程，并且所述数据感测单元和所述编程单元与所述双向内部总线通信以重新路由到所述总线读取数据和所述至少两个存储器半矩阵的编程数据。

公开(公告)号：US6137725A

公开(公告)日：2000-10-24

申请号：US203937

申请日：1998-12-02

Applicant: Fabio Tassan Caser ,  Mauro Sali ,  Marcello Cane

Inventor： Fabio Tassan Caser ,  Mauro Sali ,  Marcello Cane

IPC: G11C8/10 ,  G11C16/08 ,  G11C16/06

CPC classification number: G11C8/10 ,  G11C16/08

Abstract: The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.

Abstract translation: 本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号 和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子 矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。 耗尽晶体管的控制端构成电路的另一输入。

公开(公告)号：US6127847A

公开(公告)日：2000-10-03

申请号：US88380

申请日：1998-06-01

Applicant: Guglielmo Sirna ,  Giuseppe Palmisano ,  Mario Paparo

Inventor： Guglielmo Sirna ,  Giuseppe Palmisano ,  Mario Paparo

IPC: H03K19/018 ,  H03K19/082

CPC classification number: H03K19/01812

Abstract: A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.

Abstract translation: 一种包括输入级的高速双极至CMOS逻辑转换器电路，其包括将被连接到双极逻辑电路部分并由双极逻辑部分的电源电压提供的差分放大器，以及 输出级，其由CMOS逻辑电路部分的电压提供，插入在输入级和输出级之间的动态电平移位电路，输出级连接到CMOS逻辑电路部分。

公开(公告)号：US6115801A

公开(公告)日：2000-09-05

申请号：US49858

申请日：1998-03-27

Applicant: Paolo Rolandi

Inventor： Paolo Rolandi

IPC: G11C5/06 ,  G06F12/00

CPC classification number: G11C5/066

Abstract: A semiconductor integrated, storage circuit device having at least a first enable terminal for enabling the device, and a first number of address terminals for inputting an external address formed of a corresponding first number of bits. The device comprises a plurality of data storage elements which are addressable by an internal address formed of a second number of bits larger than said first number, and further comprises address storage elements which are coupleable with their inputs to the first enable terminal for storing additional address bits. Thus, the internal address is comprised of the external address and the additional address bits.

Abstract translation: 一种半导体集成存储电路装置，具有至少一个用于启用该装置的第一使能端子以及用于输入由相应的第一位数形成的外部地址的第一数量的地址端子。 所述设备包括多个数据存储元件，所述多个数据存储元件可由通过大于所述第一数量的第二数量位形成的内部地址寻址，并且还包括可与其输入耦合到所述第一使能端的地址存储元件，用于存储附加地址 位。 因此，内部地址由外部地址和附加地址位构成。

公开(公告)号：US6078523A

公开(公告)日：2000-06-20

申请号：US48941

申请日：1998-03-26

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C7/06 ,  G11C16/28 ,  G11C16/06

CPC classification number: G11C7/065 ,  G11C16/28

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure which has two output nodes and which includes equalization transistor of a first polarity which equalizes the two output nodes and is connected between a first branch and a second branch, in which the output nodes are arranged; the equalization transistor is driven by an equalization signal whose slope can be modulated as a function of conductivity of a memory cell of the memory device.

Abstract translation: 一种增益调制读出放大器，特别是用于存储器件的增益调制读出放大器，其包括具有两个输出节点的虚拟接地锁存器结构，该虚拟接地锁存器结构包括均衡两个输出节点并连接在第一分支和第二分支之间的第一极性的均衡晶体管， 其中输出节点被布置; 均衡晶体管由均衡信号驱动，该均衡信号的斜率可以作为存储器件的存储单元的电导率的函数进行调制。