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    Dual-domain combinational logic circuitry
    562.
    发明授权
    Dual-domain combinational logic circuitry 有权

    公开(公告)号：US11068237B1

    公开(公告)日：2021-07-20

    申请号：US16503346

    申请日：2019-07-03

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: G06F7/503 ,  G06F7/502 ,  H03K19/0185 ,  G06F9/30 ,  H03K19/00

    Abstract: A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

    MEMORY MODULE WITH DEDICATED REPAIR DEVICES
    565.
    发明申请
    MEMORY MODULE WITH DEDICATED REPAIR DEVICES 有权

    公开(公告)号：US20210133061A1

    公开(公告)日：2021-05-06

    申请号：US16670798

    申请日：2019-10-31

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

    IPC: G06F11/20 ,  G11C29/52 ,  G11C11/4093

    Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

    Memory module with reduced read/write turnaround overhead
    566.
    发明授权
    Memory module with reduced read/write turnaround overhead 有权

    公开(公告)号：US10983933B2

    公开(公告)日：2021-04-20

    申请号：US16840341

    申请日：2020-04-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Craig E. Hampel

    IPC: G06F13/16 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096 ,  G06F13/40 ,  G11C11/408 ,  G11C11/4093

    Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

    Memory component with adjustable core-to-interface data rate ratio
    567.
    发明授权
    Memory component with adjustable core-to-interface data rate ratio 有权

    公开(公告)号：US10964361B2

    公开(公告)日：2021-03-30

    申请号：US15837475

    申请日：2017-12-11

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern

    IPC: G11C7/10

    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

    MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION
    568.
    发明申请
    MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION 有权

    公开(公告)号：US20210089237A1

    公开(公告)日：2021-03-25

    申请号：US17247167

    申请日：2020-12-02

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Thomas Vogelsang

    IPC: G06F3/06 ,  G11C7/10 ,  G11C29/02 ,  G06F11/10

    Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

    Memory Controller For Selective Rank Or Subrank Access
    569.
    发明申请
    Memory Controller For Selective Rank Or Subrank Access 有权

    公开(公告)号：US20210049115A1

    公开(公告)日：2021-02-18

    申请号：US17009102

    申请日：2020-09-01

    Applicant: Rambus Inc.

    Inventor： Craig E. Hampel ,  Frederick A. Ware

    IPC: G06F13/16 ,  G06F13/42 ,  G11C5/04 ,  G11C7/10 ,  H05K1/18 ,  G06F12/1081 ,  G06F13/28

    Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

    OPTIMIZING POWER IN A MEMORY DEVICE
    570.
    发明申请
    OPTIMIZING POWER IN A MEMORY DEVICE 有权

    公开(公告)号：US20210041932A1

    公开(公告)日：2021-02-11

    申请号：US16947973

    申请日：2020-08-26

    Applicant: Rambus Inc.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

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