公开(公告)号：US20200280721A1

公开(公告)日：2020-09-03

申请号：US16874911

申请日：2020-05-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew S. Pomianowski ,  Konstantine Iourcha

IPC: H04N19/124 ,  H04N19/119 ,  H04N19/46 ,  H04N19/196 ,  H04N19/122 ,  H04N19/96 ,  H04N19/12 ,  H04N19/17 ,  H04N19/194 ,  H04N19/587 ,  H04N19/60

Abstract: An apparatus for encoding an image and an apparatus for decoding an image are presented. An image contains one or more regions. For encoding the image, the image is decomposed into one or more regions and a region is evaluated to determine whether the region meets a predetermined compressions acceptability criteria. The region is then encoded in response to the transformed and quantized region meeting the predetermined compression acceptability criteria. For decoding the image, a region of the image is selected and the selected region is decoded using metadata associated with the selected region. The metadata includes transformation quantization settings and information describing an aspect ratio used to compress the region.

公开(公告)号：US20200278947A1

公开(公告)日：2020-09-03

申请号：US16813336

申请日：2020-03-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F15/80

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

公开(公告)号：US10761736B2

公开(公告)日：2020-09-01

申请号：US16055716

申请日：2018-08-06

Applicant: ATI Technologies ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Nima Osqueizadeh ,  Paul Blinzer

IPC: G06F3/06

Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.

公开(公告)号：US20200272726A1

公开(公告)日：2020-08-27

申请号：US16709224

申请日：2019-12-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Scott MOE ,  Nicholas Penha MALAYA ,  Sudhanva GURUMURTHI ,  Naman MAHESHWARI

IPC: G06F21/45 ,  G06N3/08 ,  G06T11/00

Abstract: An apparatus includes one or more processors that are configured to determine a pixel-by-pixel bounds for a perturbed image, generate an adversarial example using an adversarial example generation technique, and modify the adversarial example to generate the perturbed image based on the pixel-by-pixel bounds. When an initial perturbed image does not reside within the pixel-by-pixel bounds, the one or more processors adjust the initial perturbed image to generate the perturbed image by a Weber-Fechner based adversarial perturbation to reside within the pixel-by-pixel bounds. The one or more processors provide the perturbed image to a computing device in an image-based Completely Automated Public Turing Test to tell Computers and Humans Apart (CAPTCHA).

公开(公告)号：US10747553B2

公开(公告)日：2020-08-18

申请号：US16167162

申请日：2018-10-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Guennadi Riguer ,  Brian K. Bennett

IPC: G06F9/448 ,  G06T15/00 ,  G09G5/36

Abstract: Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. The shader may reference a particular slot of the descriptor set using an offset, and may change shader resources by referencing a different slot of the descriptor set or by binding or rebinding a new descriptor set. A graphics pipeline may be specified by creating a pipeline object which specifies a shader and a rendering context object, and linking the pipeline object. Part or all of the pipeline may be validated, cross-validated, or optimized during linking.

公开(公告)号：US20200257796A1

公开(公告)日：2020-08-13

申请号：US16857058

申请日：2020-04-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Maurice B. Steinman

IPC: G06F21/55 ,  H04L29/06 ,  G06F21/71

Abstract: A host system-on-chip (SoC) includes a network on chip (NoC) for transmitting local traffic between internal blocks of the SoC, an external processor link for receiving messages at the host SoC from an untrusted device. A traffic controller in the host SoC that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the NoC resulting from the messages from the untrusted device.

公开(公告)号：US10742834B2

公开(公告)日：2020-08-11

申请号：US15663516

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Radhakrishna Giduthuri ,  Michael L. Schmit

IPC: H04N5/225 ,  H04N1/21 ,  G06T1/60 ,  G06T1/20 ,  G06F9/445 ,  H04N101/00

Abstract: A computer vision processing device is provided which comprises memory configured to store data and a processor. The processor is configured to store captured image data in a first buffer and acquire access to the captured image data in the first buffer when the captured image data is available for processing. The processor is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data when a last operation of the first group of operations executes.

公开(公告)号：US20200250787A1

公开(公告)日：2020-08-06

申请号：US16263709

申请日：2019-01-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Jeffrey Gongxian Cheng ,  Ahmed M. Abdelkhalek ,  Yinan Jiang ,  Xingsheng Wan ,  Anthony Asaro ,  David Martinez Nieto

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F9/38

Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.

公开(公告)号：US20200225956A1

公开(公告)日：2020-07-16

申请号：US16834834

申请日：2020-03-30

Applicant: Advanced Micro Devices, Inc.

Inventor： David N. Suggs

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0855 ,  G06F12/0862

Abstract: A system and method for using an operation (op) cache is disclosed. The system and method include an op cache for caching previously decoded instructions. The op cache includes a plurality of physically indexed and tagged instructions allowing sharing of instructions between threads. The op cache is chained through multiple ways allowing service of a plurality of instructions in a cache line. The op cache is stored between a shared operation storage and immediate/displacement storage to maximize capacity.

公开(公告)号：US10715139B2

公开(公告)日：2020-07-14

申请号：US16120836

申请日：2018-09-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Mangalore Anand ,  Jagadeesh Anathahalli Singrigowda ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K19/003 ,  H03K17/687

Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.