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公开(公告)号：US10223162B2
公开(公告)日：2019-03-05
申请号：US15097859
申请日：2016-04-13
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael T. Clark , Jay Fleischman , Thaddeus S. Fortenberry , Maurice B. Steinman
IPC: G06F12/12 , G06F9/50 , G06F12/0875 , G06F12/0811 , G06F9/455
Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.
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公开(公告)号：US08832485B2
公开(公告)日：2014-09-09
申请号：US13854616
申请日：2013-04-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
CPC classification number: G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
Abstract translation: 公开了一种用于动态控制高速缓存大小的方法和装置。 在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。 该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。
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公开(公告)号：US20180039777A1
公开(公告)日：2018-02-08
申请号：US15230388
申请日：2016-08-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Gabriel H. Loh , Maurice B. Steinman
Abstract: A host system-on-chip (SoC) includes a network on chip (NoC) for transmitting local traffic between internal blocks of the SoC, an external processor link for receiving messages at the host SoC from an untrusted device. A traffic controller in the host SoC that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the NoC resulting from the messages from the untrusted device.
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公开(公告)号：US20170031719A1
公开(公告)日：2017-02-02
申请号：US15097859
申请日：2016-04-13
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael T. Clark , Jay Fleischman , Thaddeus S. Fortenberry , Maurice B. Steinman
CPC classification number: G06F9/5016 , G06F9/45558 , G06F9/5077 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F12/121 , G06F2009/4557 , G06F2009/45579 , G06F2009/45583 , G06F2009/45591 , G06F2209/501 , G06F2209/508 , G06F2212/1041 , G06F2212/152 , G06F2212/283
Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.
Abstract translation: 用于跟踪来宾虚拟机（VM）的系统资源利用的系统，设备和方法。 可以维护计数器以跟踪在系统上执行的不同来宾VM的不同系统资源的资源利用。 当guest虚拟机启动执行时，存储的值可能被加载到资源利用率计数器中。 客机虚拟机执行时，计数器可以跟踪来宾虚拟机的资源利用率。 当客人VM终止执行时，可以将计数器值写入到与虚拟机对应的虚拟机控制块（VMCB）。 缩放因子可以应用于计数器值，以便在将值写入VMCB之前规范化值。 云计算环境可以利用跟踪机制来根据用户的服务水平协议来保证资源利用水平。
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公开(公告)号：US20130283078A1
公开(公告)日：2013-10-24
申请号：US13919306
申请日：2013-06-17
Applicant: Advanced Micro Devices, Inc
Inventor： Alexander Branover , Maurice B. Steinman , William L. Bircher
IPC: G06F1/32
CPC classification number: G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.
Abstract translation: 公开了一种用于处理节点的性能控制的装置和方法。 在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点 时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使 处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。
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Patent Agency Ranking
公开(公告)号：US20130227321A1
公开(公告)日：2013-08-29
申请号：US13854616
申请日：2013-04-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC: G06F1/32
CPC classification number: G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
Abstract translation: 公开了一种用于动态控制高速缓存大小的方法和装置。 在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。 该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。
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公开(公告)号：US20130246820A1
公开(公告)日：2013-09-19
申请号：US13889840
申请日：2013-05-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Alexander J. Branover , Ashish Jain , Ann M. Ling , Maurice B. Steinman
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/324 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
Abstract: An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components.
Abstract translation: 公开了用于动态调整处理节点和其他组件（诸如外围接口）的组件的功率限制的装置和方法。 该设备包括多个处理节点和其他组件，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置对于至少一个处理节点的第一频率限制。 对于没有可靠的功耗报告或成本或省电原因的组件，初始功率限制设置在保护带功率限制以下。 处理节点的节流量用于调整处理节点和这些组件的功率限制。
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公开(公告)号：US20230342325A1
公开(公告)日：2023-10-26
申请号：US18216908
申请日：2023-06-30
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Gordon Caruk , Maurice B. Steinman , Gerald R. Talbot , Joseph D. Macri
CPC classification number: G06F13/4282 , G06F13/1689 , G06F2213/0026
Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
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公开(公告)号：US11726915B2
公开(公告)日：2023-08-15
申请号：US16821632
申请日：2020-03-17
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Yasuko Eckert , Maurice B. Steinman , Steven Raasch
IPC: G06F12/0817 , G06F12/084
CPC classification number: G06F12/0824 , G06F12/084
Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.
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公开(公告)号：US11693813B2
公开(公告)日：2023-07-04
申请号：US16427020
申请日：2019-05-30
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Gordon Caruk , Maurice B. Steinman , Gerald R. Talbot , Joseph D. Macri
CPC classification number: G06F13/4282 , G06F13/1689 , G06F2213/0026
Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
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