VOLTAGE GAIN AMPLIFIER ARCHITECTURE FOR AUTOMOTIVE RADAR

    公开(公告)号:US20210391837A1

    公开(公告)日:2021-12-16

    申请号:US17461123

    申请日:2021-08-30

    Abstract: Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.

    DYNAMIC RANDOMIZATION OF PASSWORD CHALLENGE

    公开(公告)号:US20210365545A1

    公开(公告)日:2021-11-25

    申请号:US17396137

    申请日:2021-08-06

    Abstract: A method of operating an electronic device includes generating scramble control codes. The scramble codes are generated by generating a random number, shifting the random number to produce a shifted random number, generating control signals by selecting different subsets of the shifted random number, and generating scramble control words by selecting different subsets of the random number based upon the control signals. The method further includes receiving a password comprised of sub-words and scrambling those sub-words according to the scramble control codes, retrieving a verification word comprised of sub-words and scrambling those sub-words according to the scramble control codes, and comparing the scrambled sub-words of the password to the scrambled sub-words of the verification word to thereby authenticate an external device that provided the password.

    Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

    公开(公告)号:US11183924B2

    公开(公告)日:2021-11-23

    申请号:US17021013

    申请日:2020-09-15

    Inventor: Vikas Rana

    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

    Enhancing high-voltage startup voltage rating for PWM controllers with internal high voltage startup circuit

    公开(公告)号:US11165334B2

    公开(公告)日:2021-11-02

    申请号:US16801370

    申请日:2020-02-26

    Abstract: A power supply has a transformer with primary and secondary windings. A first terminal of the primary-winding is coupled to a power-input. A PFC includes a low-voltage circuit correcting power factor of the power signal, having a supply-input receiving a supply voltage during normal operation, a feedback-input coupled to a first terminal of the secondary-winding, and a gate-drive-output. A high-voltage startup circuit powers the low-voltage circuit during startup. Periphery circuitry includes a transient voltage suppression diode having an anode coupled to supply power to the high-voltage startup circuit and a cathode coupled to the power-input, a diode having an anode coupled to the first terminal of the secondary-winding and a cathode coupled to the supply-input of the low-voltage circuit. A capacitor is coupled between the supply-input and ground. A transistor has a drain coupled to a second terminal of the primary-winding and a gate coupled to the gate-drive-output.

    CLOCK DELAY CIRCUIT FOR CHIP RESET ARCHITECTURE

    公开(公告)号:US20210286417A1

    公开(公告)日:2021-09-16

    申请号:US17194037

    申请日:2021-03-05

    Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.

    System and method to increase display area utilizing a plurality of discrete displays

    公开(公告)号:US11093197B2

    公开(公告)日:2021-08-17

    申请号:US16045269

    申请日:2018-07-25

    Abstract: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.

    ADAPTIVE LOW POWER COMMON MODE BUFFER

    公开(公告)号:US20210250036A1

    公开(公告)日:2021-08-12

    申请号:US17245592

    申请日:2021-04-30

    Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

    SERIAL DATA INTERFACE WITH REDUCED LOOP DELAY

    公开(公告)号:US20210248104A1

    公开(公告)日:2021-08-12

    申请号:US17143679

    申请日:2021-01-07

    Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.

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