公开(公告)号：US5976927A

公开(公告)日：1999-11-02

申请号：US58120

申请日：1998-04-10

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-cheng Sung

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-cheng Sung

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L21/8247 ,  H01L21/76

CPC分类号： H01L27/10844 ,  H01L21/76202 ,  H01L27/11517

摘要： A method for forming a field oxide isolation regions of a memory array is described. The field isolation regions comprise a rectangular array of oxide islands. The oxide islands are formed by a two mask process wherein the first mask is a LOCOS hardmask which defines an array of parallel field oxide stripes. The field oxide stripes are thermally grown by a LOCOS oxidation process. A second mask, which has an array of parallel stripes perpendicular to the field oxide stripes is then patterned over the wafer. The stripes of the second mask expose a plurality of narrow sections of the field oxide stripes which are then etched by a directional plasma etch having a high selectivity of silicon oxide over silicon. The anisotropic etch segments each of the longer oxide stripes into a string of islands space apart by a narrow gap through which a robust common source line passes unencumbered by birdsbeak oxide. The edges of the field oxide at the gap have vertical walls and square corners which afford improved spacing of components in the vicinity of the gap. The method eliminates the need for a mask bias to accommodate corner rounding and birdsbeak oxide encroachment which occurs if the islands are defined by a single mask process.

摘要翻译： 描述了形成存储器阵列的场氧化物隔离区域的方法。 场隔离区域包括氧化物岛的矩形阵列。 氧化物岛通过两个掩模工艺形成，其中第一掩模是定义平行场氧化物条纹阵列的LOCOS硬掩模。 场氧化物条纹通过LOCOS氧化工艺热生长。 然后将具有垂直于场氧化物条纹的平行条纹阵列的第二掩模图案化在晶片上。 第二掩模的条纹暴露出场氧化物条纹的多个窄部分，然后通过硅上的氧化硅选择性高的定向等离子体蚀刻来蚀刻。 各向异性蚀刻将较长的氧化物条中的每一个划分成岛状空间，间隔狭窄的间隙，坚固的公共源极线穿过该间隙不受鸟笼氧化物阻碍。 间隙处的场氧化物的边缘具有垂直壁和方角，其提供间隙附近的部件的间隔改善。 该方法消除了掩模偏压的需要，以适应拐角倒圆和鸟瞰氧化物侵蚀，如果岛由单个掩模过程定义，则会发生。

公开(公告)号：US06667509B1

公开(公告)日：2003-12-23

申请号：US09590124

申请日：2000-06-09

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hong-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hong-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory. This is accomplished in two embodiments where in the first, fluorine is implanted in the first polysilicon layer to form the floating gate. It is disclosed here that the implanting of fluorine increases the oxidation rate of the polysilicon and because of the faster oxidation, the polygate bird's beak that is formed attains a relatively short and sharp in comparison with conventional beaks. This has the attendant benefit of forming a relatively small memory cell, and the concomitant reduction in the erase speed of the cell. In the second embodiment, oxygen is used with the same favorable results. A third embodiment discloses the structure of a split-gate flash memory cell having a sharp bird's beak.

摘要翻译： 提供了一种用于形成短而尖锐的门鸟喙的方法，以便增加分闸门闪存的擦除速度。 这在两个实施方案中实现，其中在第一个中，将氟注入第一多晶硅层以形成浮栅。 这里公开的是，氟的注入增加了多晶硅的氧化速率，并且由于更快的氧化，与常规的喙相比，所形成的多孔雀鸟的喙相对较短而尖锐。 这具有形成相对小的存储单元的伴随的好处，并且伴随地降低了单元的擦除速度。 在第二实施例中，使用氧气具有相同的有利结果。 第三实施例公开了具有尖锐鸟喙的分裂式闪存单元的结构。

公开(公告)号：US06635922B1

公开(公告)日：2003-10-21

申请号：US09654829

申请日：2000-09-05

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种形成尖锐的多晶硅尖端以提高分流栅闪存的速度的方法。 提供尖锐的多头尖端来代替常规的门鸟嘴（GBB），因为后者需要形成在超级集成技术的小型化电路中越来越困难的厚的多晶氧化物。 此外，众所周知，GBB在分割门闪存中的栅极边缘下侵入并降低亚微米存储器单元的可编程性。 通过高压蚀刻形成锥形浮栅，使得多晶氧化物下方的浮栅的上边缘的尖端更清晰，更坚固，因而不易受损，从而提供本发明的尖锐的多尖端 在电池的制造期间。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US06624025B2

公开(公告)日：2003-09-23

申请号：US09940158

申请日：2001-08-27

申请人： Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

发明人： Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

摘要翻译： 提供了具有倾斜沟槽源的改进的编程和擦除速度的分裂栅极闪存单元，以及其形成方法。 这通过形成两个浮动栅极和它们各自的控制栅极共享公共源极区域来实现。 在源区域中形成沟槽，并且壁倾斜以具有倾斜。 以倾斜角进行源植入，并且沟槽衬有栅极氧化物层。 随后，进行源植入物的横向扩散，然后进行热循环。 发现扩散源的横向放大基本上增加了分裂栅极闪存单元的耦合比。

公开(公告)号：US06583466B2

公开(公告)日：2003-06-24

申请号：US10117889

申请日：2002-04-08

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L27/11556 ,  H01L21/28273

摘要： A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regions are formed between the rows. A set of trenches are formed with sidewalls and a bottom in a semiconductor substrate with threshold implant regions formed in the sidewalls. Doped drain regions are formed near the surface of the substrate and doped source regions are formed in the base of the device below the trenches with oppositely doped channel regions therebetween. A tunnel oxide layer is formed over the substrate including the trenches aside from FOX regions. Floating gates of doped polysilicon are formed over the tunnel oxide layer in the trenches. An interelectrode dielectric layer covers the floating gate layer. Control gate electrodes of doped polysilicon are formed over the interelectrode dielectric layer. Spacers are formed adjacent to the sidewalls of the control gate electrode.

摘要翻译： 垂直晶体管存储器件包括以行和列形成的FET单元，其中相对于列正交布置的行。 单行中的几个单元具有共同的源极区域，并且相邻的单元具有共同的漏极区域，在行之间形成FOX区域。 在半导体衬底中形成具有在侧壁中形成的阈值注入区域的侧壁和底部的一组沟槽。 在衬底的表面附近形成掺杂的漏极区，并且掺杂源极区形成在沟槽下方的器件的底部，其间具有相反的掺杂沟道区。 在包括除FOX区域之外的沟槽的衬底上形成隧道氧化物层。 掺杂多晶硅的浮栅形成在沟槽中的隧道氧化物层上。 电极间电介质层覆盖浮栅层。 掺杂多晶硅的控制栅电极形成在电极间电介质层上。 间隔件邻近控制栅电极的侧壁形成。

公开(公告)号：US06559501B2

公开(公告)日：2003-05-06

申请号：US09850639

申请日：2001-05-07

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.

摘要翻译： 公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。 通常用单栅极器件（例如逻辑器件）执行致敏。 在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。 此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。 在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。 因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。

公开(公告)号：US06544828B1

公开(公告)日：2003-04-08

申请号：US10044860

申请日：2001-11-07

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

IPC分类号： H01L218234

CPC分类号： H01L29/402 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/4238

摘要： A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过在漏极侧的浅沟槽隔离区域的边缘处形成导电场板来提高高电压NMOS器件的耐久性和鲁棒性的方法。 活性区域通过衬底中的隔离区域分离。 在活性区域上生长栅极氧化物层。 导电层沉积在栅极氧化物层上并被图案化以在有源区域中形成栅电极，并且在有源区域的漏极侧上的隔离边缘处形成与有源区域和隔离区域重叠的导电条带，其中导电条 在集成电路器件的制造中减小隔离边缘的电场。

公开(公告)号：US06504206B2

公开(公告)日：2003-01-07

申请号：US10147221

申请日：2002-05-16

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7887

摘要： In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and extend partially under the sidewalls to allow the operation of the floating gates with respect to the buried bit line which act as drains and sources. A control gate is deposited over a row of sidewalls orthogonal to the bit lines and extending the length of a flash memory word line. The polysilicon sidewall split gate flash memory cells are programmed, read and erased by a combination of voltages applied to the control gate and the bit lines partially underlying the sidewalls.

公开(公告)号：US06483159B1

公开(公告)日：2002-11-19

申请号：US09617426

申请日：2000-07-14

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.

摘要翻译： 一种分裂门EEPROM存储器件，形成在掺杂硅半导体衬底上，起始于其上形成有未掺杂的第一多晶硅层的初始氧化物层。 在未掺杂的第一多晶硅层上的多晶硅氧化物硬掩模，用于构图初始氧化物层和未掺杂的第一多晶硅层，然后将其从未掺杂的第一多晶硅层和衬底上的初始氧化物层进行蚀刻以形成浮置栅电极堆叠 。 然后形成隧道氧化物层和掺杂多晶硅并将它们图案化成控制栅极电极堆叠，其中控制栅极电极堆叠相对于浮动栅电极堆叠位于分离栅极配置中。

公开(公告)号：US06420233B1

公开(公告)日：2002-07-16

申请号：US09766860

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

IPC分类号： H01L29336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，采用掺杂多晶硅浮栅，其具有中间环状部分，其掺杂浓度高于周边环形 掺杂多晶硅浮栅电极的一部分。 掺杂多晶硅浮置栅电极的中心环形部分内的较高掺杂剂浓度提供了分裂栅极场效应晶体管（FET）器件的增强的编程速度特性。 在掺杂多晶硅浮置栅电极的外围环形部分内的较低掺杂剂浓度在分裂栅极场效应晶体管（FET）器件的制造的某些情况下在分裂栅极场效应晶体管（FET）器件内提供增强的擦除速度特性。