公开(公告)号：US06420233B1

公开(公告)日：2002-07-16

申请号：US09766860

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

IPC分类号： H01L29336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，采用掺杂多晶硅浮栅，其具有中间环状部分，其掺杂浓度高于周边环形 掺杂多晶硅浮栅电极的一部分。 掺杂多晶硅浮置栅电极的中心环形部分内的较高掺杂剂浓度提供了分裂栅极场效应晶体管（FET）器件的增强的编程速度特性。 在掺杂多晶硅浮置栅电极的外围环形部分内的较低掺杂剂浓度在分裂栅极场效应晶体管（FET）器件的制造的某些情况下在分裂栅极场效应晶体管（FET）器件内提供增强的擦除速度特性。

公开(公告)号：US06465836B2

公开(公告)日：2002-10-15

申请号：US09821199

申请日：2001-03-29

申请人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

发明人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L29/7887 ,  H01L29/42336

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，在半导体衬底内形成沟槽，其沟槽内的沟槽区域完全包含在分离栅极场内 效应晶体管（FET）器件。 类似地，在分裂栅极场效应晶体管内还形成有沟槽内的浮置栅电极，并且在沟槽内覆盖沟道区的下部子部分。 最后，浮栅电极依次形成在沟槽内垂直和水平重叠的覆盖通道的上部子部分的控制栅电极。 分离栅场效应晶体管（FET）器件制造具有增强的面密度和增强的性能。

公开(公告)号：US06297099B1

公开(公告)日：2001-10-02

申请号：US09765045

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  Y10S438/981

摘要： A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.

摘要翻译： 一种制造浮栅/字线装置的方法，包括以下步骤。 提供半导体结构。 在半导体结构上方形成浮栅部分。 浮动门部分具有侧壁和顶面。 多晶氧化物部分形成在浮动栅极的顶表面上。 在半导体结构，多晶氧化物部分和多晶氧化物部分之上形成多层氧化物层。 所述多晶硅氧化物层具有初始厚度，并且包括：与所述浮动栅极部分相邻的所述半导体结构的至少一部分上的字线区域部分; 浮动部分侧壁上的侧壁区域部分; 以及多个氧化物部分上方的顶部。 互折层氧化物层的顶部的初始厚度减小到第二厚度，而不会减小多晶氧化物字线区域部分的初始厚度或多余氧化物侧壁区域部分的明显部分。 在多晶硅层上形成多晶硅层。 将结构图案化以形成浮动栅/字线装置。

公开(公告)号：US06544828B1

公开(公告)日：2003-04-08

申请号：US10044860

申请日：2001-11-07

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

IPC分类号： H01L218234

CPC分类号： H01L29/402 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/4238

摘要： A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过在漏极侧的浅沟槽隔离区域的边缘处形成导电场板来提高高电压NMOS器件的耐久性和鲁棒性的方法。 活性区域通过衬底中的隔离区域分离。 在活性区域上生长栅极氧化物层。 导电层沉积在栅极氧化物层上并被图案化以在有源区域中形成栅电极，并且在有源区域的漏极侧上的隔离边缘处形成与有源区域和隔离区域重叠的导电条带，其中导电条 在集成电路器件的制造中减小隔离边缘的电场。

公开(公告)号：US06468863B2

公开(公告)日：2002-10-22

申请号：US09761276

申请日：2001-01-16

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.

摘要翻译： 在制造分裂栅极场效应晶体管的方法和使用该方法制造的分裂栅极场效应晶体管的两者中，采用形成为覆盖浮置栅极的第一部分和半导体的第一部分的图案化氮化硅阻挡介电层 衬底邻近浮动栅极的第一部分。 在半导体衬底的第一部分内，当制造分裂栅极场效应晶体管时，最终形成源极/漏极区域，尤其是源极区域。 图案化的氮化硅阻挡介电层在制造分离栅场效应晶体管离子注入损坏浮栅和浮栅电极边缘的氧化损失时禁止。

公开(公告)号：US06724036B1

公开(公告)日：2004-04-20

申请号：US09654776

申请日：2000-09-05

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.

摘要翻译： 描述了具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极闪存单元。 在衬底中的浅沟槽隔离（STI）中形成非常规的高隔离氧化层。 在STI之间的空间中的深开口共形地衬有多晶硅以形成在开口上方延伸的浮动栅极。 保形隔离层氧化物对整个浮动栅线进行排列。 一层多晶硅覆盖了间隔栅极氧化物并向下突出到开口中，以形成一个与浮动栅极增加耦合的控制栅极。

公开(公告)号：US5970341A

公开(公告)日：1999-10-19

申请号：US988772

申请日：1997-12-11

申请人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.

摘要翻译： 通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。 在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。 在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。 形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。 衬底中的源极/漏极区域与浮栅电极层自对准。 通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图。 在其中形成控制门孔。 在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

公开(公告)号：US6133097A

公开(公告)日：2000-10-17

申请号：US133969

申请日：1998-08-14

申请人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。 栅电极中心的图案源极线槽向下堆叠到衬底。 在源线插槽的底部形成源区。 在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 形成自对准漏极区。

公开(公告)号：US6078076A

公开(公告)日：2000-06-20

申请号：US317645

申请日：1999-05-24

申请人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.

摘要翻译： 通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。 在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。 在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。 形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。 衬底中的源极/漏极区域与浮栅电极层自对准。 通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图在其中形成控制栅极孔。 在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

公开(公告)号：US06326662B1

公开(公告)日：2001-12-04

申请号：US09633643

申请日：2000-08-07

申请人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。 栅电极中心的图案源极线槽向下堆叠到衬底。 在源线插槽的底部形成源区。 在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 形成自对准漏极区。