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    INTEGRATED CIRCUIT SELECTIVE SCALING
    51.
    发明申请
    INTEGRATED CIRCUIT SELECTIVE SCALING 有权
    集成电路选择性缩放

    公开(公告)号：US20080148210A1

    公开(公告)日：2008-06-19

    申请号：US12035572

    申请日：2008-02-22

    Applicant: Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    Inventor： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

    Abstract translation: 本发明包括通过以下方式选择性地缩放集成电路（IC）设计的解决方案：层，区域或单元，或它们的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了使设计人员提高产量的需要。

    Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
    55.
    发明授权
    Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
    冗余微环结构用于集成电路物理设计过程及其形成方法

    公开(公告)号：US08234594B2

    公开(公告)日：2012-07-31

    申请号：US11552225

    申请日：2006-10-24

    Applicant: Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    Inventor： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    IPC: G06F17/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

    Abstract translation: 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和位于距离第二线的第一距离的第四线 在第二级线路上。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔大致轴向对准第一通孔。 第三通过在第四线的第二位置连接第三和第四导线。 在第二位置连接第一和第四导线的第四通孔，第四通孔与第三通孔大致轴向对齐。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

    Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
    56.
    发明授权
    Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
    用于集成电路物理设计过程中使用的冗余微环结构的设计结构及其形成方法

    公开(公告)号：US07984394B2

    公开(公告)日：2011-07-19

    申请号：US11955580

    申请日：2007-12-13

    Applicant: Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    Inventor： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

    Abstract translation: 一种用于集成电路的设计结构，该集成电路包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线，以及位于第一距离处的第四线 第二根电线在第二级线路上。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。 第三通过在第四线的第二位置连接第三和第四导线。 第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

    Systematic yield in semiconductor manufacture
    58.
    发明授权
    Systematic yield in semiconductor manufacture 失效
    半导体制造系统产量

    公开(公告)号：US07725864B2

    公开(公告)日：2010-05-25

    申请号：US11854000

    申请日：2007-09-12

    Applicant: Paul H. Bergeron ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    Inventor： Paul H. Bergeron ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.

    Abstract translation: 提供三维结构，其提高半导体器件中某些结构的制造成品率。 三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。 因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。 提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

    Content based yield prediction of VLSI designs
    59.
    发明授权
    Content based yield prediction of VLSI designs 失效
    基于内容的VLSI设计的产量预测

    公开(公告)号：US07661081B2

    公开(公告)日：2010-02-09

    申请号：US12101599

    申请日：2008-04-11

    Applicant: Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    Inventor： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

    Abstract translation: 一种用于预测VLSI设计产量的集成电路系统和程序产品。 提供一种集成电路系统，包括用于通过电路类型识别和集成集成电路设计中所包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

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