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公开(公告)号：US08705300B1
公开(公告)日：2014-04-22
申请号：US12850528
申请日：2010-08-04
申请人： Yanzhong Xu , Jeffrey T. Watt
发明人： Yanzhong Xu , Jeffrey T. Watt
CPC分类号： G11C29/08 , G11C5/147 , G11C11/417 , G11C29/021 , G11C29/028
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays with memory cells arranged in rows and columns. Address lines may be associated with each row of memory cells and data lines may be associated with each column of memory cells. Precharge driver circuitry may be used to precharge the data lines to a precharge voltage prior to performing read operations. The integrated circuit may contain core logic that is powered using a core logic power supply voltage. The precharge voltage may be reduced with respect to the core logic power supply voltage. Each address transistor may have a body bias terminal. The integrated circuit may contain programmable voltage regulator circuitry that produces a body bias for the address transistors based on a body bias setting stored in nonvolatile memory on the integrated circuit.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有存储器阵列，存储器单元以行和列排列。 地址线可以与每行存储器单元相关联，并且数据线可以与每列存储器单元相关联。 预充电驱动器电路可以用于在执行读取操作之前将数据线预充电到预充电电压。 集成电路可能包含使用核心逻辑电源电压供电的核心逻辑。 可以相对于核心逻辑电源电压来减小预充电电压。 每个地址晶体管可以具有体偏置端子。 集成电路可以包含可编程电压调节器电路，其基于存储在集成电路中的非易失性存储器中的体偏置设置而产生用于地址晶体管的体偏置。
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公开(公告)号：US08630113B1
公开(公告)日：2014-01-14
申请号：US12277411
申请日：2008-11-25
申请人： Yanzhong Xu , Jeffrey T. Watt
发明人： Yanzhong Xu , Jeffrey T. Watt
IPC分类号： G11C11/34
CPC分类号： G11C11/34
摘要： An integrated circuit (IC) includes a memory circuit. The memory circuit includes a plurality of thyristors. The plurality of thyristors are coupled in tandem.
摘要翻译： 集成电路（IC）包括存储电路。 存储电路包括多个晶闸管。 多个晶闸管串联耦合。
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公开(公告)号：US08611137B2
公开(公告)日：2013-12-17
申请号：US13304226
申请日：2011-11-23
申请人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
发明人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
IPC分类号： G11C11/00
CPC分类号： G11C11/52 , B82Y10/00 , G11C13/025 , G11C23/00 , H01H1/0094 , H01H1/20 , H01H59/0009 , H01L27/101 , H01L27/11
摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.
摘要翻译： 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。
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公开(公告)号：US08355292B2
公开(公告)日：2013-01-15
申请号：US12571143
申请日：2009-09-30
申请人： Yanzhong Xu , Jeffrey T. Watt
发明人： Yanzhong Xu , Jeffrey T. Watt
IPC分类号： G11C5/14
CPC分类号： G11C11/4125 , H03K19/0033
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.
摘要翻译： 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管。 为了克服将数据写入存储元件的困难，可以调整提供给阵列的一个或多个信号的信号强度。 在为每个存储元件供电时使用两个正电源电压。 电源电压之一可能相对于另一个电源电压暂时降低，以增强数据加载操作期间的写入裕度。 可以以这种方式调整的其他信号强度包括其他电源信号，数据信号电平，地址和清除信号幅度以及接地信号强度。 可调电源电路和数据读写控制电路可用于进行这些信号强度的调整。
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公开(公告)号：US20120319236A1
公开(公告)日：2012-12-20
申请号：US13161893
申请日：2011-06-16
申请人： Shuxian Chen , Jeffrey T. Watt
发明人： Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01L27/06 , H01F27/28 , H01L21/768
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0046 , H01F2017/0073 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.
摘要翻译： 电感器可以由包括相互缠绕的导线的导电路径形成。 在导电路径中可能有两个，三个或多于三个相互缠绕的导线。 导电线可以由集成电路的电介质堆叠中的导电结构形成。 电介质堆叠可以包括包括导电迹线的金属层，并且可以包括通孔层，其包括用于互连迹线的通孔。 相互缠绕的导线可以由金属和通孔层中的导电结构形成。 在交叉区域中，导线可彼此交叉而不彼此电连接。 通孔可用于将多层迹线耦合在一起以降低线路电阻。
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公开(公告)号：US08295029B1
公开(公告)日：2012-10-23
申请号：US13018351
申请日：2011-01-31
申请人： Shuxian Chen , Jeffrey T. Watt
发明人： Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01G4/228
CPC分类号： H01G4/38 , H01G4/005 , H01G4/01 , H01G4/228 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A multi-segment capacitor fabricated on a semiconductor substrate includes MxN capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.
摘要翻译： 制造在半导体衬底上的多段电容器包括以M行和N列的矩阵排列的M×N电容器段。 每个电容器段包括优选由金属线制成的两组导电指状物。 金属线指以这样的方式分布在多个金属层内，使得特定金属层内的两个相邻的平行金属线指电绝缘并连接到电容器的不同端子。 此外，至少两个不同金属层内的平行金属线指的纵向轴线在相同的电容器段内彼此不平行。
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公开(公告)号：US08116048B1
公开(公告)日：2012-02-14
申请号：US12577547
申请日：2009-10-12
IPC分类号： H02H3/22
CPC分类号： H02H3/22
摘要： In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.
摘要翻译： 在传统的差分输出电路中，输出端连接到差分对晶体管的漏极，晶体管的源极在第一个节点连接在一起。 晶体管的主体连接到具有不同于第一节点的电位的第二节点。 在HBM ESD事件发生的情况下，放电可能通过差分晶体管发生，从而导致其中的一个被破坏。 为了降低这种放电的可能性，在优选实施例中，提供开关以在感测到ESD事件时将每个差分晶体管的主体连接到第一节点。 在替代实施例中，当感测到ESD事件时，提供开关来将第一节点连接到第二节点。
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公开(公告)号：US08077500B2
公开(公告)日：2011-12-13
申请号：US12820410
申请日：2010-06-22
申请人： Yanzhong Xu , Jeffrey T. Watt
发明人： Yanzhong Xu , Jeffrey T. Watt
CPC分类号： G11C11/4125 , H03K19/0033
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.
摘要翻译： 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管。 为了克服将数据写入存储元件的困难，可以调整提供给阵列的一个或多个信号的信号强度。 在为每个存储元件供电时使用两个正电源电压。 电源电压之一可能相对于另一个电源电压暂时降低，以增强数据加载操作期间的写入裕度。 可以以这种方式调整的其他信号强度包括其他电源信号，数据信号电平，地址和清除信号幅度以及接地信号强度。 可调电源电路和数据读写控制电路可用于进行这些信号强度的调整。
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公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
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公开(公告)号：US07955923B1
公开(公告)日：2011-06-07
申请号：US12845337
申请日：2010-07-28
IPC分类号： H01L21/8238
CPC分类号： H01L29/6659 , H01L27/0277 , H01L29/1083 , H01L29/1087 , H01L2924/14
摘要： A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors. In these embodiments, either an N+/PLDD diode or an implanted diode is formed in place of one of the transistors.
摘要翻译： 通过在I / O焊盘和下拉装置的主体之间连接二极管，为下拉装置提供触发电路。 在一个实施例中，下拉装置形成为单个阱中的多个分立晶体管。 每个晶体管的漏极通过镇流电阻连接到I / O焊盘; 并且每个晶体管的源极通过镇流电阻器连接到地。 触发电路是形成在与晶体管不同的阱中的二极管。 二极管的阴极连接到I / O焊盘，阳极通过位于晶体管之间的中心抽头连接到晶体管。 优选地，晶体管是形成在P阱中的NMOS晶体管。 有利地，二极管是N + / PLDD二极管。 或者，二极管是N + / P二极管，其中P区由ESD注入形成。 在其他实施例中，二极管形成在与晶体管相同的阱中。 在这些实施例中，形成N + / PLDD二极管或注入二极管代替晶体管之一。
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