公开(公告)号：US08116117B2

公开(公告)日：2012-02-14

申请号：US12632018

申请日：2009-12-07

Applicant: Woo-Yeong Cho ,  Ki-Sung Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Jun-Soo Bae

Inventor： Woo-Yeong Cho ,  Ki-Sung Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Jun-Soo Bae

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2211/5634

Abstract: Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.

Abstract translation: 公开了一种驱动多电平可变电阻存储器件的方法。 一种驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定电阻窗，预期电阻 窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少量的写入电流，以便改变可变电阻存储单元的电阻。

公开(公告)号：US08035145B2

公开(公告)日：2011-10-11

申请号：US12773451

申请日：2010-05-04

Applicant: Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

Inventor： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

IPC: H01L21/02

CPC classification number: G11C11/15 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3281 ,  H01F41/302 ,  H01L43/08

Abstract: A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

Abstract translation: 提供磁存储器件。 磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。 在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。 在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。 在存储和无引导模式之间插入一个自由的反转模式。 自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。

公开(公告)号：US07787278B2

公开(公告)日：2010-08-31

申请号：US12229341

申请日：2008-08-22

Applicant: Jun-Soo Bae ,  Hideki Horii ,  Mi-Lim Park

Inventor： Jun-Soo Bae ,  Hideki Horii ,  Mi-Lim Park

IPC: G11C17/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004

Abstract: Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.

Abstract translation: 提供一种电阻变量存储装置及其操作方法。 电阻可变存储器件在顶部电极和底部电极之间具有相变材料。 在用于操作电阻可变存储器的方法中，写入电流沿从顶部电极到底部电极的方向施加，并且读取电流沿着从底部电极到顶部电极的方向施加。 通过施加写入电流来编程相变材料，并且通过施加读取电流来抑制相变材料的电阻漂移。

公开(公告)号：US07778066B2

公开(公告)日：2010-08-17

申请号：US12228914

申请日：2008-08-18

Applicant: Hideki Horii ,  Jun-Soo Bae

Inventor： Hideki Horii ,  Jun-Soo Bae

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: Provided is a method of programming a resistance variable memory device. The resistance variable memory device includes a memory cell having multi states and a write driver outputting a program pulse for programming the memory cell into one of the multi states. The method of programming the resistance variable memory device includes applying a first program pulse to the resistance variable memory device and applying a second program pulse to a memory cell when the memory cell is programmed into an intermediate state. When the first program pulse is a reset pulse, the reset pulse is an over program pulse, that is, an over reset pulse. Therefore, the resistance variable memory device can secure a sufficient read margin as well as improve a resistance drift margin.

Abstract translation: 提供了一种编程电阻变量存储器件的方法。 电阻可变存储器件包括具有多态的存储器单元和写入驱动器，其输出用于将存储器单元编程为多态的其中一个的编程脉冲。 编程电阻可变存储器件的方法包括：当存储器单元被编程到中间状态时，将第一编程脉冲施加到电阻可变存储器件并向存储单元施加第二编程脉冲。 当第一个编程脉冲是复位脉冲时，复位脉冲是过程编程脉冲，即过复位脉冲。 因此，电阻可变存储器件可以确保足够的读取余量以及改善电阻漂移裕度。

公开(公告)号：US07767568B2

公开(公告)日：2010-08-03

申请号：US11905244

申请日：2007-09-28

Applicant: Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

Inventor： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

IPC: H01L21/3205

CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

Abstract: A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.

Abstract translation: 提供了一种相变存储器件及其制造方法。 具有第一表面的第一电极设置在基板上。 具有与第一表面不同的第二表面的第二电极在基板上。 第二电极可以与第一电极间隔开。 可以对应于第一电极形成第三电极。 可以对应于第二电极形成第四电极。 可以在第一表面和第三电极之间插入第一相变图案。 可以在第二表面和第四电极之间插入第二相变图案。 第一和第二相变图案的上表面可以在同一平面上。

公开(公告)号：US07692176B2

公开(公告)日：2010-04-06

申请号：US11193961

申请日：2005-07-29

Applicant: Yong-Ho Ha ,  Bong-Jin Kuh ,  Ji-Hye Yi ,  Jun-Soo Bae

Inventor： Yong-Ho Ha ,  Bong-Jin Kuh ,  Ji-Hye Yi ,  Jun-Soo Bae

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Abstract translation: 相变存储器件包括电连接到衬底中的晶体管的杂质区的下电极和在下电极上包括第一相变材料的编程层图案。 包含具有比第一相变材料低的热导率的材料的绝热层图案在编程层图案上，上电极在绝热层图案上。

公开(公告)号：US07645619B2

公开(公告)日：2010-01-12

申请号：US12073098

申请日：2008-02-29

Applicant: Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

Inventor： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

IPC: H01L21/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract translation: 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

公开(公告)号：US20090052236A1

公开(公告)日：2009-02-26

申请号：US12229341

申请日：2008-08-22

Applicant: Jun-Soo Bae ,  Hideki Horii ,  Mi-Lim Park

Inventor： Jun-Soo Bae ,  Hideki Horii ,  Mi-Lim Park

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004

Abstract: Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.

Abstract translation: 提供一种电阻变量存储装置及其操作方法。 电阻可变存储器件在顶部电极和底部电极之间具有相变材料。 在用于操作电阻可变存储器的方法中，写入电流沿着从顶部电极到底部电极的方向施加，并且读取电流沿着从底部电极到顶部电极的方向施加。 通过施加写入电流来编程相变材料，并且通过施加读取电流来抑制相变材料的电阻漂移。

公开(公告)号：US20080093590A1

公开(公告)日：2008-04-24

申请号：US11974774

申请日：2007-10-16

Applicant: Dong-Ho Ahn ,  Hideki Horii ,  Jong-Chan Shin ,  Jun-Soo Bae ,  Hyeong-Geun An

Inventor： Dong-Ho Ahn ,  Hideki Horii ,  Jong-Chan Shin ,  Jun-Soo Bae ,  Hyeong-Geun An

IPC: H01L45/00 ,  H01L21/06

CPC classification number: H01L45/143 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  Y10S438/90

Abstract: Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.

Abstract translation: 提供了一种相变存储器件及其形成方法。 根据相变存储器，第一插头电极和第二插头电极在模具绝缘层中彼此间隔开。 相变图案设置在模具绝缘层上。 相变图案接触第一插头电极的顶部和第二插头电极的顶部的第一部分。 互连电连接到第二插头电极的顶部的第二部分。

公开(公告)号：US20080068879A1

公开(公告)日：2008-03-20

申请号：US11881062

申请日：2007-07-25

Applicant: Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

Inventor： Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

IPC: G11C11/00 ,  H01L45/00

CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

Abstract: A phase change memory device may include an integrated circuit substrate and first and second phase change memory elements on the integrated circuit substrate. The first phase change memory element may include a first phase change material having a first crystallization temperature. The second phase change memory element may include a second phase change material having a second crystallization temperature. Moreover, the first and second crystallization temperatures may be different so that the first and second phase change memory elements are programmable at different temperatures. Related methods and systems are also discussed.

Abstract translation: 相变存储器件可以包括集成电路衬底以及集成电路衬底上的第一和第二相变存储元件。 第一相变存储元件可以包括具有第一结晶温度的第一相变材料。 第二相变存储元件可以包括具有第二结晶温度的第二相变材料。 此外，第一和第二结晶温度可以不同，使得第一和第二相变存储元件可在不同温度下编程。 还讨论了相关方法和系统。