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公开(公告)号：US09225253B2
公开(公告)日：2015-12-29
申请号：US13658640
申请日：2012-10-23
Applicant: Microchip Technology, Inc.
Inventor： Jimes Lei
CPC classification number: H02M3/33569 , H02M3/158 , H02M3/337 , H02M7/103 , H02M2001/0045 , H02M2001/007
Abstract: A switching linear amplifier has a DC-DC converter to increase a low input DC voltage to a first high voltage DC. A high voltage high frequency inverter is coupled to the DC-DC converter to generate high voltage pulses. A multistage voltage multiplier is coupled to the high voltage high frequency inverter to generate a second high voltage DC. A controlled charge and discharge circuit is coupled to the multistage voltage multiplier to drive a capacitive load.
Abstract translation: 开关线性放大器具有DC-DC转换器，以将低输入DC电压增加到第一高压DC。 高压高频逆变器耦合到DC-DC转换器以产生高电压脉冲。 多级电压倍增器耦合到高压高频逆变器以产生第二高压DC。 受控充电和放电电路耦合到多级电压倍增器以驱动电容性负载。
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52.发明授权Low dropout light emitting diode (LED) ballast circuit and method therefor 有权低压差发光二极管（LED）镇流器电路及其方法公开(公告)号：US09041313B2
公开(公告)日：2015-05-26
申请号：US13871360
申请日：2013-04-26
Applicant: Microchip Technology, Inc.
Inventor： Alexander Mednik
CPC classification number: H05B33/0815 , H05B33/0818 , Y02B20/346
Abstract: A ballast circuit for a Light Emitting Diode (LED) has a regulator element coupled to the LED and to an input voltage source. A control circuit is coupled to the LED and to an input voltage source. A first switching device is coupled in series with the regulator element. A second switching device is coupled to the input voltage and the control circuit.
Abstract translation: 用于发光二极管（LED）的镇流器电路具有耦合到LED和输入电压源的调节器元件。 控制电路耦合到LED和输入电压源。 第一开关装置与调节器元件串联耦合。 第二开关器件耦合到输入电压和控制电路。
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公开(公告)号：US12175116B2
公开(公告)日：2024-12-24
申请号：US17669995
申请日：2022-02-11
Applicant: Microchip Technology Inc.
Inventor： Christopher I. W. Norrie
IPC: G06F3/06
Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.
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公开(公告)号：US11526343B2
公开(公告)日：2022-12-13
申请号：US16577251
申请日：2019-09-20
Applicant: Microchip Technology Inc.
Inventor： Nilesh Rajbharti , Mark Ennamorato
Abstract: A system and method for improved evaluation of semiconductor hardware is provided. The system comprises a firmware repository server, which firmware repository server comprises a plurality of firmware packages for the one or more evaluation hardware boards. The firmware repository server is further configured to: receive a firmware request for a user evaluation hardware board from a first of the client devices, search the plurality of firmware packages for compatible firmware packages for the user evaluation hardware board, generate a catalog of the compatible firmware packages for the user evaluation hardware board, transmit the catalog to the first client device, receive a request for a user selected firmware package from the catalog of compatible firmware packages, and to transmit firmware of the user selected firmware package to the client device for installation on the user evaluation hardware board.
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公开(公告)号：US20220374169A1
公开(公告)日：2022-11-24
申请号：US17398091
申请日：2021-08-10
Applicant: Microchip Technology Inc.
Inventor： Lorenzo Zuolo , Rino Micheloni
Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.
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Patent Agency Ranking
公开(公告)号：US20220342844A1
公开(公告)日：2022-10-27
申请号：US17701582
申请日：2022-03-22
Applicant: Microchip Technology Inc.
Inventor： Christopher I. W. NORRIE
IPC: G06F15/80
Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.
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公开(公告)号：US11424902B2
公开(公告)日：2022-08-23
申请号：US17242493
申请日：2021-04-28
Applicant: Microchip Technology Inc.
Inventor： Atanu Chattopadhyay , Andras de Koos
IPC: H04L7/00 , H04L43/0864
Abstract: System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal.
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公开(公告)号：US20220262434A1
公开(公告)日：2022-08-18
申请号：US17736563
申请日：2022-05-04
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.
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公开(公告)号：US11323123B2
公开(公告)日：2022-05-03
申请号：US16827691
申请日：2020-03-23
Applicant: Microchip Technology Inc.
Inventor： Mike Willingham
Abstract: A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when a rollover event of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to a VCO clock cycle phase fraction value when the rollover detector circuit has detected the interpolator rollover event.
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公开(公告)号：US20220058488A1
公开(公告)日：2022-02-24
申请号：US17148200
申请日：2021-01-13
Applicant: Microchip Technology Inc.
Inventor： Lorenzo Zuolo , Rino Micheloni
Abstract: A method includes storing configuration files of a Multi-Core Neural Network Inference (MCNNI) model having Independent Categorized-Core-Portions (ICCP's). Each ICCP corresponds to one of a plurality of categories for each parameter. A first plurality of weighting values on each row of the weighting matrix of the MCNNI model have a nonzero value and a second plurality of weighting values on each row having a value of zero. The configuration files are loaded into a neural network engine. The operation of the integrated circuit device is monitored to identify a usage value corresponding to each of the parameters. A single neural network operation is performed using the usage values as input to generate, at the output neurons of each ICCP, output values indicating an estimation of one or more variable. The output values of the ICCP that corresponds to the input usage values are identified and are sent as output.
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