公开(公告)号：US6148371A

公开(公告)日：2000-11-14

申请号：US881727

申请日：1997-06-25

申请人： Ricky C. Hetherington ,  Sharad Mehrotra ,  Ramesh Panwar

发明人： Ricky C. Hetherington ,  Sharad Mehrotra ,  Ramesh Panwar

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0859

摘要： A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.

摘要翻译： 与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的设备接收数据访问的第一非阻塞缓存。 第二非阻塞高速缓存耦合到第一非阻塞高速缓存以服务第一非阻塞高速缓存中的未命中。 耦合到第二非阻塞缓存的数据返回路径将从第二非阻塞高速缓存返回的数据与第一非阻塞高速缓存和产生对第一非阻塞高速缓存的访问的设备耦合。

公开(公告)号：US6094719A

公开(公告)日：2000-07-25

申请号：US881958

申请日：1997-06-25

申请人： Ramesh Panwar

发明人： Ramesh Panwar

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30014 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having four possible register dependencies is converted into two microinstructions which are processed normally within the processor. The first microinstruction is coded to perform the arithmetic operation specified by the single-precision instruction using the first and second source registers specified and storing the result in a phantom register. The second microinstruction is coded for merging the contents of the phantom register and the destination register specified. Each microinstruction has at most two possible register dependencies, thereby reducing the total number of register dependencies which the processor is required to track.

摘要翻译： 在具有混合到双精度浮点寄存器中的单精度浮点寄存器的无序处理器中，具有四个可能的寄存器依赖性的单精度浮点算术运算被转换成两个微指令，它们在 处理器。 第一个微指令被编码为使用指定的第一个和第二个源寄存器执行由单精度指令指定的算术运算，并将结果存储在幻像寄存器中。 第二个微指令被编码用于合并幻象寄存器的内容和指定的目标寄存器。 每个微指令至多有两个可能的寄存器依赖关系，从而减少了处理器需要跟踪的寄存器依赖关系的总数。

公开(公告)号：US6058466A

公开(公告)日：2000-05-02

申请号：US881732

申请日：1997-06-24

申请人： Ramesh Panwar ,  Joseph I. Chamdani

发明人： Ramesh Panwar ,  Joseph I. Chamdani

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3806 ,  G06F9/3802 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3863

摘要： A system of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services is placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

摘要翻译： 在具有共享执行资源的动态可配置多处理器中执行编码指令的系统，包括在引导多处理器时将第一处理器置于活动状态的步骤。 响应于处理器创建命令，第二处理器被置于活动状态。 当第一或第二处理器遇到必须由片外高速缓存服务的高速缓存未命中时，处理器需要服务处于休眠状态，在该状态下禁止该处理器的指令取出。 当第一或第二处理器遇到必须由主存储器服务的高速缓存未命中时，需要服务的处理器通过在睡眠状态下从处理器中冲洗所有指令而置于休眠状态，并且禁用在处理器中的指令获取 睡眠状态

公开(公告)号：US6052775A

公开(公告)日：2000-04-18

申请号：US881723

申请日：1997-06-25

申请人： Ramesh Panwar ,  Ricky C. Hetherington

发明人： Ramesh Panwar ,  Ricky C. Hetherington

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861

摘要： A method for operating a processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

摘要翻译： 一种用于操作处理器的方法，所述处理器使用接收所述编码指令并发出执行指令的指令调度单元执行编码指令。 重播信令装置产生指示在预定时间内什么时候指令无法正常执行的信号。 响应于信令装置的指令调度单元内的重放装置然后重新发出用于执行的指令。

公开(公告)号：US6035374A

公开(公告)日：2000-03-07

申请号：US881239

申请日：1997-06-25

申请人： Ramesh Panwar ,  Joseph I. Chamdani

发明人： Ramesh Panwar ,  Joseph I. Chamdani

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

摘要翻译： 一种在具有共享执行资源的动态可配置多处理器中执行编码指令的方法，包括在所述多处理器引导时将第一处理器置于活动状态的步骤。 响应于处理器创建命令，第二处理器被置于活动状态。 当第一或第二处理器遇到必须由片外高速缓存服务的高速缓存未命中时，处理器需要服务处于休眠状态，在该状态下禁止该处理器的指令取出。 当第一或第二处理器遇到必须由主存储器服务的高速缓存未命中时，处理器要求服务I处于睡眠状态，通过在处于休眠状态的状态下冲洗所有指令并禁止在处理器中取出指令 睡眠状态

公开(公告)号：US5987594A

公开(公告)日：1999-11-16

申请号：US881726

申请日：1997-06-25

申请人： Ramesh Panwar ,  Ricky C. Hetherington

发明人： Ramesh Panwar ,  Ricky C. Hetherington

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861

摘要： A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

摘要翻译： 一种使用指令调度单元执行编码指令并且发出执行指令的处理器。 重播信令装置产生指示在预定时间内什么时候指令无法正常执行的信号。 响应于信令装置的指令调度单元内的重放装置然后重新发出用于执行的指令。

公开(公告)号：US5898853A

公开(公告)日：1999-04-27

申请号：US882173

申请日：1997-06-25

申请人： Ramesh Panwar ,  Dani Y. Dakhil

发明人： Ramesh Panwar ,  Dani Y. Dakhil

IPC分类号： G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an instruction identifier and the destination register specified by the live instruction. The table can also contain information about the age of the entry, the validity of the entry, and the process which the entry is associated. A dependency between instructions is determined by one or more comparators comparing the destination register to the source registers of the current instruction. True dependencies are distinguished from false dependencies using the age information, the validity information, and the process information.

摘要翻译： 在执行指令或乱序指令的处理器中，依赖表跟踪当前指令和实时指令之间的指令依赖关系。 该表包含指令标识符和由实时指令指定的目标寄存器。 该表还可以包含关于条目的年龄，条目的有效性以及条目相关联的进程的信息。 指令之间的相关性由一个或多个将目的地寄存器与当前指令的源寄存器进行比较的比较器确定。 使用年龄信息，有效性信息和过程信息将真依赖性与假依赖关系区分开。

公开(公告)号：US09021582B2

公开(公告)日：2015-04-28

申请号：US11739365

申请日：2007-04-24

申请人： Gary Goldman ,  Philip A. Thomas ,  Ramesh Panwar

发明人： Gary Goldman ,  Philip A. Thomas ,  Ramesh Panwar

IPC分类号： G06F11/00 ,  H04L29/06

CPC分类号： H04L63/0245 ,  H04L63/1416

摘要： This disclosure describes techniques of determining whether a symbol stream includes a pattern defined by a regular expression. As described herein, the regular expression may be represented using a non-deterministic finite automaton (NFA). A plurality of states in the NFA may be evaluated in parallel. These states may be associated with a plurality of symbol positions in a symbol stream. Evaluating a plurality of states and symbols in parallel may allow for faster determinations of whether the symbol stream includes the pattern defined by the regular expression.

摘要翻译： 本公开描述了确定符号流是否包括由正则表达式定义的模式的技术。 如本文所述，正则表达式可以使用非确定性有限自动机（NFA）来表示。 可以并行评估NFA中的多个状态。 这些状态可以与符号流中的多个符号位置相关联。 并行地评估多个状态和符号可以允许更快地确定符号流是否包括由正则表达式定义的模式。

公开(公告)号：US08571034B2

公开(公告)日：2013-10-29

申请号：US13097770

申请日：2011-04-29

申请人： Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan ,  Jean-Marc Frailong

发明人： Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan ,  Jean-Marc Frailong

IPC分类号： H04L12/28

CPC分类号： H04L45/00 ,  H04L45/12 ,  H04L49/1515 ,  H04L49/503

摘要： In one embodiment, an apparatus can include a policy vector module configured to retrieve a compressed policy vector based on a portion of a data packet received at a multi-stage switch. The apparatus can also include a decompression module configured to receive the compressed policy vector and configured to define a decompressed policy vector based on the compressed policy vector. The decompressed policy vector can define a combination of bit values associated with a policy.

摘要翻译： 在一个实施例中，装置可以包括策略向量模块，其被配置为基于在多级交换机处接收到的数据分组的一部分来检索压缩策略向量。 该装置还可以包括解压缩模块，其被配置为接收压缩的策略向量并且被配置为基于压缩的策略向量来定义解压缩的策略向量。 解压缩的策略向量可以定义与策略相关联的比特值的组合。

公开(公告)号：US08370528B2

公开(公告)日：2013-02-05

申请号：US12843710

申请日：2010-07-26

申请人： Mark Bryers ,  Elango Ganesan ,  Frederick Gruner ,  David Hass ,  Robert Hathaway ,  Ramesh Panwar ,  Ricardo Ramirez ,  Abbas Rashid ,  Mark Vilas ,  Yen Lee ,  John Phillips ,  Yuhong Andy Zhou ,  Gregory G. Spurrier ,  Sankar Ramanoorthi ,  Michael Freed

发明人： Mark Bryers ,  Elango Ganesan ,  Frederick Gruner ,  David Hass ,  Robert Hathaway ,  Ramesh Panwar ,  Ricardo Ramirez ,  Abbas Rashid ,  Mark Vilas ,  Nazar Zaidi ,  Yen Lee ,  Chau Anh Ngoc Nguyen ,  John Phillips ,  Yuhong Andy Zhou ,  Gregory G. Spurrier ,  Sankar Ramanoorthi ,  Michael Freed

IPC分类号： G06F15/16

CPC分类号： H04L47/125 ,  H04L29/06 ,  H04L63/0485

摘要： A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.