公开(公告)号：US08295655B2

公开(公告)日：2012-10-23

申请号：US12310431

申请日：2007-08-24

Applicant: Sasikanth Manipatruni ,  Qianfan Xu ,  Michal Lipson

Inventor： Sasikanth Manipatruni ,  Qianfan Xu ,  Michal Lipson

IPC: G02F1/035

CPC classification number: G02B6/12007 ,  G02B6/29343 ,  G02B6/4215 ,  G02F1/025 ,  G02F2203/15

Abstract: An optical modulator includes a ring resonator with a waveguide adjacent to and optically coupled to the micro-ring resonator. A p-i-n junction is formed about the ring resonator. An optional additional doped region may be formed opposite the waveguide from the ring resonator and when combined with the p-i-n junction forms a nearly closed p-i-n junction about the ring resonator. The ring resonator may be a silicon micro-ring resonator. Multiple different resonant frequency resonators may be coupled to the waveguide along with different detectors to multiplex light on the waveguide. The spectrum of the resonator may be controlled by an applied voltage. A prepulsing device may be used to enhance electrical transitions to enhance the speed of the modulator.

Abstract translation: 光调制器包括环形谐振器，其具有与微环谐振器相邻并且光耦合的微波环。 围绕环形谐振器形成p-i-n结。 可选的附加掺杂区域可以形成为与环形谐振器相对的波导，并且当与p-i-n结结合形成围绕环形谐振器的近似闭合的p-i-n结。 环形谐振器可以是硅微环谐振器。 多个不同的谐振频率谐振器可以与不同的检测器耦合到波导，以在波导上复用光。 谐振器的频谱可以通过施加的电压来控制。 可以使用预脉冲装置来增强电转换以提高调制器的速度。

公开(公告)号：US20100098372A1

公开(公告)日：2010-04-22

申请号：US12310431

申请日：2007-08-24

Applicant: Sasikanth Manipatruni ,  Qianfan Xu ,  Michal Lipson

Inventor： Sasikanth Manipatruni ,  Qianfan Xu ,  Michal Lipson

IPC: G02F1/025

CPC classification number: G02B6/12007 ,  G02B6/29343 ,  G02B6/4215 ,  G02F1/025 ,  G02F2203/15

Abstract: An optical modulator includes a ring resonator with a waveguide adjacent to and optically coupled to the micro-ring resonator. A p-i-n junction is formed about the ring resonator. An optional additional doped region may be formed opposite the waveguide from the ring resonator and when combined with the p-i-n junction forms a nearly closed p-i-n junction about the ring resonator. The ring resonator may be a silicon micro-ring resonator. Multiple different resonant frequency resonators may be coupled to the waveguide along with different detectors to multiplex light on the waveguide. The spectrum of the resonator may be controlled by an applied voltage. A prepulsing device may be used to enhance electrical transitions to enhance the speed of the modulator.

Abstract translation: 光调制器包括环形谐振器，其具有与微环谐振器相邻并且光耦合的微波环。 围绕环形谐振器形成p-i-n结。 可选的附加掺杂区域可以形成为与环形谐振器相对的波导，并且当与p-i-n结结合形成围绕环形谐振器的近似闭合的p-i-n结。 环形谐振器可以是硅微环谐振器。 多个不同的谐振频率谐振器可以与不同的检测器耦合到波导，以在波导上复用光。 谐振器的频谱可以通过施加的电压来控制。 可以使用预脉冲装置来增强电转换以提高调制器的速度。

公开(公告)号：US20200091407A1

公开(公告)日：2020-03-19

申请号：US16130905

申请日：2018-09-13

Applicant: Huichu LIU ,  Tanay KARNIK ,  Sasikanth MANIPATRUNI ,  Daniel MORRIS ,  Kaushik VAIDYANATHAN ,  Ian YOUNG

Inventor： Huichu LIU ,  Tanay KARNIK ,  Sasikanth MANIPATRUNI ,  Daniel MORRIS ,  Kaushik VAIDYANATHAN ,  Ian YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18 ,  H01L43/06

Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.

公开(公告)号：US20190087717A1

公开(公告)日：2019-03-21

申请号：US16081575

申请日：2016-04-01

Applicant: Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov

IPC: G06N3/063 ,  G06N3/08

Abstract: One embodiment provides a four stable state neuron. The four stable state neuron includes a plurality of input elements and a plurality of coupling channels. Each input element is coupled to a respective coupling channel and each input element is to scale a respective two-dimensional input signal by a weight. The four stable state neuron further includes a first output element coupled to the plurality of coupling channels. The first output element is to receive the plurality of weighted two-dimensional input signals and to generate a two-dimensional output signal based, at least in part, on a threshold value.

公开(公告)号：US20190056885A1

公开(公告)日：2019-02-21

申请号：US16160482

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/1081 ,  G06N3/04

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

公开(公告)号：US20190042159A1

公开(公告)日：2019-02-07

申请号：US16146878

申请日：2018-09-28

Applicant: Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

Inventor： Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

IPC: G06F3/06 ,  H03K3/03 ,  G11C7/10

Abstract: Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.

公开(公告)号：US20160377669A1

公开(公告)日：2016-12-29

申请号：US14749324

申请日：2015-06-24

Applicant: Sasikanth Manipatruni ,  Chia-Ching Lin ,  Yih Wang ,  Ian A. Young

Inventor： Sasikanth Manipatruni ,  Chia-Ching Lin ,  Yih Wang ,  Ian A. Young

IPC: G01R31/12 ,  G11C29/00 ,  G01R29/26 ,  G11C11/16

CPC classification number: G01R29/26 ,  G01R31/129 ,  G01R31/2879 ,  G11C11/1697 ,  G11C29/50 ,  G11C2029/5002

Abstract: Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed.

Abstract translation: 实施例包括用于测试磁随机存取存储器（MRAM）的一个或多个磁隧道结（MTJ）的测试电路。 测试电路可以测量时域中的MTJ的1 / f噪声，并确定1 / f噪声的功率谱密度（PSD）。 测试电路可以基于PSD估计MTJ和/或MRAM的一个或多个参数。 例如，测试电路可以基于PSD来确定诸如Hooge alpha参数的噪声参数，并且可以基于1 / f参数估计MTJ和/或MRAM的一个或多个参数。 可以描述和要求保护其他实施例。

公开(公告)号：US09460768B2

公开(公告)日：2016-10-04

申请号：US13997050

申请日：2013-03-14

Applicant: Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/18

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/18 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of such arrays are described. For example, a bit cell for a non-volatile memory includes a magnetic tunnel junction (MTJ) stack disposed above a substrate and having a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer. The bit cell also includes a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack.

Abstract translation: 描述了实现基于旋转霍尔磁隧道结（MTJ）的设备和这种阵列的操作方法的交叉点阵列磁阻随机存取存储器（MRAM）。 例如，用于非易失性存储器的位单元包括设置在衬底上方的磁性隧道结（MTJ）堆叠，并且具有设置在设置在固定磁性层上方的电介质层上方的自由磁性层。 位单元还包括设置在MTJ堆叠的自由磁性层上方的旋转霍尔金属电极。

公开(公告)号：US09362074B2

公开(公告)日：2016-06-07

申请号：US13996507

申请日：2013-03-14

Applicant: Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

Inventor： Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

IPC: H01H51/22 ,  H01H59/00 ,  B82Y10/00 ,  H01H1/00 ,  H01H9/02

CPC classification number: H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

Abstract translation: 描述了基于纳米线的机械开关装置。 例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。 纳米线具有锚固部分和悬挂部分。 第一栅电极邻近空隙设置，并与纳米线隔开。 第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

公开(公告)号：US09355242B2

公开(公告)日：2016-05-31

申请号：US13717433

申请日：2012-12-17

Applicant: Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

Inventor： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

IPC: G06F21/44 ,  G06F21/10 ,  G06F21/35

CPC classification number: G06F21/44 ,  G06F21/10 ,  G06F21/35

Abstract: Managing and accessing personal data is described. In one example, an apparatus has an application processor, a memory to store data, a receive and a transmit array coupled to the application processor to receive data to store in the memory and to transmit data stored in the memory through a wireless interface, and an inertial sensor to receive user commands to authorize the processor to receive and transmit data through the receive and transmit array.

Abstract translation: 描述管理和访问个人数据。 在一个示例中，设备具有应用处理器，用于存储数据的存储器，耦合到应用处理器的接收和发送阵列，以接收存储在存储器中的数据并通过无线接口传输存储在存储器中的数据，以及 惯性传感器，用于接收用户命令，以授权处理器通过接收和发送阵列接收和发送数据。