METHOD AND APPARATUS FOR PERFORMING ACCESS MANAGEMENT OF MEMORY DEVICE IN HOST PERFORMANCE BOOSTER ARCHITECTURE WITH AID OF DEVICE SIDE TABLE INFORMATION ENCODING AND DECODING

    公开(公告)号:US20240111451A1

    公开(公告)日:2024-04-04

    申请号:US17959308

    申请日:2022-10-04

    Inventor: Yu-Chih Lin

    CPC classification number: G06F3/0658 G06F3/0607 G06F3/0679

    Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

    Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit of a memory controller

    公开(公告)号:US11901961B2

    公开(公告)日:2024-02-13

    申请号:US17951090

    申请日:2022-09-22

    Inventor: Fu-Jen Shih

    CPC classification number: H04B17/11 H04B17/21 H04J3/04

    Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

    METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK (LDPC) CODE

    公开(公告)号:US20240030939A1

    公开(公告)日:2024-01-25

    申请号:US18220464

    申请日:2023-07-11

    Inventor: Duen-Yih TENG

    CPC classification number: H03M13/1108 H03M13/1174

    Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time. The non-sequential selection strategy indicates an arbitrary selection combination of the chunks in the codeword, which is different from that under the sequential selection strategy.

    METHOD AND APPARATUS FOR PERFORMING DATA RETENTION MANAGEMENT OF MEMORY DEVICE WITH AID OF PRE-SHUTDOWN CONTROL

    公开(公告)号:US20240028198A1

    公开(公告)日:2024-01-25

    申请号:US17870861

    申请日:2022-07-22

    Inventor: Tsung-Chieh Yang

    CPC classification number: G06F3/0607 G06F3/0656 G06F3/0679

    Abstract: A method for performing data retention management of a memory device with aid of pre-shutdown control and associated apparatus are provided. The method may include: receiving a predetermined host command from a host device; in response to the predetermined host command, performing a re-programming procedure on the NV memory, for enhancing data storage reliability of the memory device, for example, reading stored data from at least one source location within the at least one NV memory element to prepare re-programming data according to the stored data, and programming the re-programming data into at least one destination location within the at least one NV memory element to be replacement of the stored data; and in response to the re-programming procedure being completed, sending completion information of the predetermined host command to the host device, to allow the host device to trigger the shutdown of the memory device.

    Data storage device and non-volatile memory control method

    公开(公告)号:US11875058B2

    公开(公告)日:2024-01-16

    申请号:US17648679

    申请日:2022-01-24

    CPC classification number: G06F3/0659 G06F3/0619 G06F3/0679

    Abstract: A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.

    Data storage device and selecting bad data column method thereof

    公开(公告)号:US11874737B2

    公开(公告)日:2024-01-16

    申请号:US17715061

    申请日:2022-04-07

    Inventor: Sheng-Yuan Huang

    Abstract: A selecting bad data column method suitable for a data storage device is provided. The data storage device includes a control unit and a data storage medium. The selecting method performed by the control unit includes: reading written data of each data column as read data; comparing the read data and the written data of each data column to calculate an average number of error bits of each data column; determining whether the average number of error bits of each data column is greater than or equal to a predetermined value; and recording a data column as a bad data column when the average number of error bits of the data column is greater than or equal to the predetermined value. In this way, in order to avoid the problems that the error correction code can't be corrected or the correction capability is excessively consumed.

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