公开(公告)号：US20240111451A1

公开(公告)日：2024-04-04

申请号：US17959308

申请日：2022-10-04

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0607 ,  G06F3/0679

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

公开(公告)号：US20240103732A1

公开(公告)日：2024-03-28

申请号：US18142590

申请日：2023-05-03

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0646 ,  G06F3/0653 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

公开(公告)号：US11933847B2

公开(公告)日：2024-03-19

申请号：US17737351

申请日：2022-05-05

Applicant: Silicon Motion, Inc.

Inventor： Han-Chih Tsai ,  Ming-Kun Chung

IPC: G06F11/00 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/10 ,  G06F11/263 ,  G06F11/273 ,  G06F13/38

CPC classification number: G01R31/318597 ,  G01R31/318307 ,  G01R31/318572 ,  G06F11/1004 ,  G06F11/263 ,  G06F11/273 ,  G06F13/382

Abstract: The invention relates to an apparatus and a system for debugging a solid-state disk (SSD) device. The apparatus includes a Joint Test Action Group (JTAG) add-on board; and a Raspberry Pi. The Raspberry Pi includes a General-Purpose Input/Output (GPIO) interface (I/F), coupled to the JTAG add-on board; and a processing unit, coupled to the GPIO I/F. The processing unit is arranged operably to: simulate to issue a plurality of JTAG command through the GPIO I/F to the SSD device for dumping data generated by the SSD device during operation from the SSD device.

公开(公告)号：US11914901B2

公开(公告)日：2024-02-27

申请号：US17852403

申请日：2022-06-29

Applicant: Silicon Motion, Inc.

Inventor： Tsu-Han Lu ,  Hsiao-Chang Yen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

公开(公告)号：US11901961B2

公开(公告)日：2024-02-13

申请号：US17951090

申请日：2022-09-22

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen Shih

IPC: H04B17/11 ,  H04J3/04 ,  H04B17/21

CPC classification number: H04B17/11 ,  H04B17/21 ,  H04J3/04

Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

公开(公告)号：US20240045798A1

公开(公告)日：2024-02-08

申请号：US18380568

申请日：2023-10-16

Applicant: SILICON MOTION INC.

Inventor： Chao-Kuei Hsieh

IPC: G06F12/02 ,  G11C7/20 ,  G06F3/06 ,  G06F3/08 ,  G11C7/10 ,  G11C16/16 ,  G11C16/26

CPC classification number: G06F12/0246 ,  G11C7/20 ,  G06F3/0679 ,  G06F3/08 ,  G11C7/1063 ,  G11C7/109 ,  G11C16/16 ,  G11C16/26

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

公开(公告)号：US20240030939A1

公开(公告)日：2024-01-25

申请号：US18220464

申请日：2023-07-11

Applicant: Silicon Motion, Inc.

Inventor： Duen-Yih TENG

IPC: H03M13/11

CPC classification number: H03M13/1108 ,  H03M13/1174

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time. The non-sequential selection strategy indicates an arbitrary selection combination of the chunks in the codeword, which is different from that under the sequential selection strategy.

公开(公告)号：US20240028198A1

公开(公告)日：2024-01-25

申请号：US17870861

申请日：2022-07-22

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0656 ,  G06F3/0679

Abstract: A method for performing data retention management of a memory device with aid of pre-shutdown control and associated apparatus are provided. The method may include: receiving a predetermined host command from a host device; in response to the predetermined host command, performing a re-programming procedure on the NV memory, for enhancing data storage reliability of the memory device, for example, reading stored data from at least one source location within the at least one NV memory element to prepare re-programming data according to the stored data, and programming the re-programming data into at least one destination location within the at least one NV memory element to be replacement of the stored data; and in response to the re-programming procedure being completed, sending completion information of the predetermined host command to the host device, to allow the host device to trigger the shutdown of the memory device.

公开(公告)号：US11875058B2

公开(公告)日：2024-01-16

申请号：US17648679

申请日：2022-01-24

Applicant: Silicon Motion, Inc.

Inventor： Po-Sheng Chou ,  Hsiang-Yu Huang

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

Abstract: A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.

公开(公告)号：US11874737B2

公开(公告)日：2024-01-16

申请号：US17715061

申请日：2022-04-07

Applicant: Silicon Motion, Inc.

Inventor： Sheng-Yuan Huang

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0772

Abstract: A selecting bad data column method suitable for a data storage device is provided. The data storage device includes a control unit and a data storage medium. The selecting method performed by the control unit includes: reading written data of each data column as read data; comparing the read data and the written data of each data column to calculate an average number of error bits of each data column; determining whether the average number of error bits of each data column is greater than or equal to a predetermined value; and recording a data column as a bad data column when the average number of error bits of the data column is greater than or equal to the predetermined value. In this way, in order to avoid the problems that the error correction code can't be corrected or the correction capability is excessively consumed.