公开(公告)号：US07105370B2

公开(公告)日：2006-09-12

申请号：US11017615

申请日：2004-12-20

申请人： Stefan Bader ,  Michael Fehrer ,  Berthold Hahn ,  Volker Härle ,  Hans-Jürgen Lugauer

发明人： Stefan Bader ,  Michael Fehrer ,  Berthold Hahn ,  Volker Härle ,  Hans-Jürgen Lugauer

IPC分类号： H01L21/00

CPC分类号： B82Y20/00 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/0079 ,  H01S5/34333

摘要： A method for fabricating a radiation-emitting semiconductor chip having a thin-film element based on III–V nitride semiconductor material includes the steps of depositing a layer sequence of a thin-film element on an epitaxy substrate. The thin-film element is joined to a carrier, and the epitaxy substrate is removed from the thin-film element. The epitaxy substrate has a substrate body made from PolySiC or PolyGaN or from SiC, GaN or sapphire, which is joined to a grown-on layer by a bonding layer, and on which the layer sequence of the thin-film element is deposited by epitaxy.

摘要翻译： 一种制造具有基于III-V族氮化物半导体材料的薄膜元件的辐射发射半导体芯片的方法包括以下步骤：在外延衬底上沉积薄膜元件层序列。 将薄膜元件接合到载体上，并且将外延基板从薄膜元件移除。 外延衬底具有由PolySiC或PolyGaN制成的衬底主体或由SiC，GaN或蓝宝石构成的衬底主体，其通过结合层与生长层接合，并且薄膜元件的层序列通过外延沉积 。

公开(公告)号：US06927155B2

公开(公告)日：2005-08-09

申请号：US10488379

申请日：2002-09-02

申请人： Hans-Juergen Lugauer ,  Stefan Bader

发明人： Hans-Juergen Lugauer ,  Stefan Bader

IPC分类号： H01L21/205 ,  C23C16/04 ,  C23C16/30 ,  C30B25/02 ,  H01L21/033 ,  H01L21/20 ,  H01L33/00 ,  H01L21/28 ,  H01L21/3205

CPC分类号： C30B29/406 ,  C23C16/042 ,  C23C16/303 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02472 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0334 ,  H01L33/007 ,  Y10S438/933

摘要： In the process for producing low-defect semiconductor layers based on III-V nitride semiconductor material, a substrate (1) made from a material which is not based on III-V nitride semiconductors is provided, and then a mask layer (2) is applied to the substrate in order to form unmasked regions (2c) and masked regions (2a, 2b) on the substrate. Then, starting from the unmasked regions (2c) of the substrate (1), the III-V nitride semiconductor layer (3) is grown. To avoid the formation of stress-induced cracks during the cooling phase from the growth temperature to room temperature, the mask layer (2) is formed on the substrate (1) in such a manner that some of the masked regions (2b) are wide enough to prevent the III-V nitride semiconductor layer (3) from growing together over these wide masked regions (2b), whereas the III-V nitride semiconductor layer does grow together only over the other, narrow masked regions (2a).

摘要翻译： 在基于III-V族氮化物半导体材料制造低缺陷半导体层的工艺中，提供由不是基于III-V族氮化物半导体的材料制成的衬底（1），然后将掩模层（2） 施加到衬底上以在衬底上形成未掩蔽区域（2c）和掩模区域（2a，2b）。 然后，从衬底（1）的未掩蔽区域（2c）开始，生长III-V族氮化物半导体层（3）。 为了避免在从生长温度到室温的冷却阶段期间形成应力引起的裂纹，掩模层（2）以这样的方式形成在基板（1）上，使得一些掩模区域（2b）为 足够宽以防止III-V族氮化物半导体层（3）在这些宽掩蔽区域（2b）上一起生长，而III-V族氮化物半导体层确实仅在另一个狭窄掩模区域（2a）上生长， 。