公开(公告)号：US20170025307A1

公开(公告)日：2017-01-26

申请号：US15119304

申请日：2015-01-09

申请人： SUNEDISON SEMICONDUCTOR LIMITED

发明人： Michael J. Ries ,  Jeffrey Louis Libbert ,  Charles R. Lottes

IPC分类号： H01L21/762 ,  H01L23/00

CPC分类号： H01L21/76254 ,  H01L21/0455 ,  H01L21/2253 ,  H01L21/2258 ,  H01L21/265 ,  H01L24/83 ,  H01L2224/83054 ,  H01L2224/83085 ,  H01L2224/83236 ,  H01L2224/83893

摘要： Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.

摘要翻译： 公开了制备层状半导体结构的方法。 所述方法可以包括通过退火离子注入的施主晶片来预处理离子注入的施主晶片，以使得一部分离子在晶片接合之前扩散。 供体结构可以结合到手柄结构并且在不将离子重新注入到供体结构内的情况下被切割。

公开(公告)号：US20160340799A1

公开(公告)日：2016-11-24

申请号：US15157745

申请日：2016-05-18

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： John Allen Pitney

IPC分类号： C30B25/12 ,  C30B29/06 ,  C23C16/458

CPC分类号： C30B25/12 ,  C23C16/4584 ,  C30B29/06

摘要： A susceptor supports a semiconductor wafer and includes a substantially cylindrical body comprising an outer rim having an upper surface. The body also includes a recess extending into the body from the upper surface to a recess floor such that the recess is sized and shaped for receiving the wafer therein. The body further includes a ledge extending between the rim and the recess floor. The ledge includes a ramp comprising a first surface, a second surface, and a third surface. The first surface is oriented at a first angle with respect to the upper surface; the second surface is oriented at a second angle oriented with respect to the upper surface; and the third surface is oriented at a third angle with respect to the upper surface. Further, the second angle is greater than the first angle.

摘要翻译： 感受体支撑半导体晶片并且包括基本上圆柱形的主体，其包括具有上表面的外边缘。 主体还包括从上表面延伸到凹部底部的凹部，使得凹部的尺寸和形状用于在其中容纳晶片。 身体还包括在边缘和凹陷地板之间延伸的凸缘。 所述突出部包括包括第一表面，第二表面和第三表面的坡道。 第一表面相对于上表面以第一角度定向; 所述第二表面以相对于所述上表面定向的第二角度定向; 并且第三表面相对于上表面以第三角度定向。 此外，第二角度大于第一角度。

公开(公告)号：US20160276209A1

公开(公告)日：2016-09-22

申请号：US15070060

申请日：2016-03-15

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Alex Usenko

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76254

摘要： A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.

摘要翻译： 提供了一种制备用于绝缘体上半导体结构的高电阻率硅处理衬底的方法。 处理衬底被准备为在衬底区域内包含热稳定的电荷载流子阱，该区域将处于最终的绝缘体上半导体结构的掩埋氧化物层（BOX）或其附近。 通过使用至少两种不同能量进行氢离子注入，然后进行2步热处理，制造包含稳定载流子阱的手柄基板。 由此制备的热稳定缺陷结构在至少1180℃的温度下退火是稳定的。缺陷结构包括通过位错相互连接的纳米腔的三维网络。 该晶片可以用作制造绝缘体上硅（SOI）晶片并进一步制造射频（RF）半导体器件的处理晶片。

公开(公告)号：US20160071760A1

公开(公告)日：2016-03-10

申请号：US14835093

申请日：2015-08-25

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Qingmin Liu

IPC分类号： H01L21/762 ,  H01L21/324 ,  H01L21/02 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L21/76254 ,  H01L21/02112 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/324 ,  H01L27/12 ,  H01L29/0649

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

摘要翻译： 提供了一种多层复合结构体及其制备方法。 多层复合结构包括具有至少约500欧姆 - 厘米的最小体积电阻率的半导体处理衬底; 与半导体处理衬底接触的IVA族氮化物层，选自碳氮化物，氮化硅，及其组合的IVA族氮化物层; 与IVA族氮化物层接触的电介质层; 以及与电介质层接触的半导体器件层。

公开(公告)号：US20160056840A1

公开(公告)日：2016-02-25

申请号：US14464301

申请日：2014-08-20

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Markus Jan Peter Siegert

IPC分类号： H03M7/30 ,  G06F3/06

CPC分类号： H03M7/30 ,  G06F7/483

摘要： A computer-implemented method for arranging numeric data for compression is described. The method is implemented using a computing device in communication with a memory and a measurement device. The method includes receiving, by the computing device and from the measurement device, numeric data that includes a sequence of numbers, each number including at least a first byte followed by a second byte. The method additionally includes arranging the first bytes into a first contiguous set, arranging the second bytes into a second contiguous set, and storing the first contiguous set and the second contiguous set in a file in the memory, such that the first contiguous set is contiguous with the second contiguous set.

摘要翻译： 描述用于排列用于压缩的数字数据的计算机实现的方法。 该方法使用与存储器和测量装置通信的计算装置来实现。 该方法包括由计算设备和测量设备接收包括数字序列的数字数据，每个数字至少包括第一个字节和第二个字节。 该方法还包括将第一字节排列成第一连续集合，将第二字节排列成第二连续集合，以及将第一连续集合和第二连续集合存储在存储器中的文件中，使得第一连续集合是连续的 与第二个连续的集合。

公开(公告)号：US09180569B2

公开(公告)日：2015-11-10

申请号：US14107806

申请日：2013-12-16

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Peter D. Albrecht ,  Sumeet S. Bhagavat

IPC分类号： B24B37/04 ,  B24B7/22 ,  H01L21/306 ,  H01L21/66 ,  B24B37/08 ,  B24B37/12

CPC分类号： B24B7/228 ,  B24B37/08 ,  B24B37/12 ,  H01L21/30625 ,  H01L22/12

摘要： A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate.

摘要翻译： 用于抛光晶片表面的压板具有反应板，抛光板和气囊。 反应板具有顶部和底部表面，并且限定纵向轴线。 抛光板与反应板同轴设置。 抛光板具有第二顶表面和第二底表面。 第二顶表面邻近反应板的底表面。 气囊沿着反应板的顶表面或底表面的径向外部同轴地定位。 气囊与抛光板连接，能够使抛光板相对于反应板的底面膨胀而变形。

公开(公告)号：US20150126017A1

公开(公告)日：2015-05-07

申请号：US14597946

申请日：2015-01-15

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Anca Stefanescu

IPC分类号： H01L21/84 ,  H01L21/762

CPC分类号： H01L21/84 ,  B32B43/006 ,  B32B2310/028 ,  B32B2457/14 ,  H01L21/67057 ,  H01L21/67092 ,  H01L21/76254 ,  Y10T156/1126 ,  Y10T156/1928

摘要： Methods for the ultrasonic cleaving of bonded wafer pairs include positioning the bonded wafer pair in a wafer holder disposed in a tank containing a volume of liquid and ultrasonically agitating the volume of liquid in the tank with an ultrasonic agitator. The ultrasonic agitation of the volume of liquid cleaves the bonded wafer pair into a handle wafer and a silicon-on-insulator wafer.

摘要翻译： 用于超声波切割接合的晶片对的方法包括将结合的晶片对定位在设置在包含一定体积液体的罐中的晶片保持器中，并用超声波搅拌器超声波地搅拌槽中的液体体积。 液体体积的超声波搅拌将接合的晶片对切割成处理晶片和绝缘体上硅晶片。

公开(公告)号：US20150104926A1

公开(公告)日：2015-04-16

申请号：US14510929

申请日：2014-10-09

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Jeffrey L. Libbert ,  Shilpi Vaypayee

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： A method of preparing a high resistivity single crystal semiconductor handle wafer comprising implanting He ions through a front surface of the high resistivity single crystal semiconductor handle wafer, which is followed by an anneal sufficient to form a nanocavity layer in the damage region formed by He ion implantation. The anneal may be prior to or concurrent with thermal oxidation to prepare a front oxidized surface layer.

摘要翻译： 一种制备高电阻率单晶半导体处理晶片的方法，其包括通过高电阻率单晶半导体处理晶片的前表面注入He离子，随后退火足以在由He离子形成的损伤区域中形成纳米腔层 植入。 退火可以在热氧化之前或同时进行，以制备正面氧化的表面层。

公开(公告)号：US10699908B2

公开(公告)日：2020-06-30

申请号：US15577515

申请日：2016-05-26

申请人： SunEdison Semiconductor Limited

发明人： Guoqiang David Zhang ,  Mark Crooks ,  Tracy Michelle Ragan

IPC分类号： H01L21/66 ,  H01L21/321 ,  H01L21/306 ,  H01L21/304 ,  H01L21/02 ,  B24B53/017

摘要： A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. The silicon layer has a substantially uniform thickness. The silicon layer is polished to smooth the silicon layer such that the thickness is substantially uniform after polishing.

公开(公告)号：US20200035544A1

公开(公告)日：2020-01-30

申请号：US16594188

申请日：2019-10-07

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Henry Frank Erk ,  Sasha Kweskin ,  Jeffrey L. Libbert ,  Mayank Bulsara

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

摘要： A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.