公开(公告)号：US08139423B2

公开(公告)日：2012-03-20

申请号：US12939614

申请日：2010-11-04

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/06

CPC classification number: H03M9/00 ,  G11C7/1087 ,  G11C7/1096 ,  H03K3/356121 ,  H03K5/1534

Abstract: A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to generate an alignment signal in response to a transition timing of a data strobe signal. The duration signal generation unit is configured to generate a duration signal which is enabled during a predetermined duration in response to a write command. The data input clock pulse generation unit is configured to generate a data input clock pulse for transferring data to a global line in response to the alignment signal within an enable duration of the duration signal.

Abstract translation: 写驱动装置包括缓冲单元，持续时间信号生成单元和数据输入时钟脉冲生成单元。 缓冲单元被配置为响应于数据选通信号的转变定时产生对准信号。 持续时间信号生成单元被配置为产生响应于写入命令在预定持续时间期间使能的持续时间信号。 数据输入时钟脉冲生成单元被配置为响应于持续时间信号的使能持续时间内的对准信号而生成用于将数据传送到全局线的数据输入时钟脉冲。

公开(公告)号：US20110218297A1

公开(公告)日：2011-09-08

申请号：US13038926

申请日：2011-03-02

Applicant: Jong-Seong KIM ,  Woo-Jae LEE ,  Nam-Seok ROH ,  Sang-IL KIM ,  Min-Ho YOON ,  Young Tak SONG ,  Tae Jin KANG ,  Suk Heung OH ,  Seung-Jae LEE ,  Hye Jin KIM ,  Jin Ju YU ,  Dong Hyun YU ,  Young Sik YOON ,  Jong Hwan LEE

Inventor： Jong-Seong KIM ,  Woo-Jae LEE ,  Nam-Seok ROH ,  Sang-IL KIM ,  Min-Ho YOON ,  Young Tak SONG ,  Tae Jin KANG ,  Suk Heung OH ,  Seung-Jae LEE ,  Hye Jin KIM ,  Jin Ju YU ,  Dong Hyun YU ,  Young Sik YOON ,  Jong Hwan LEE

IPC: C08L1/02 ,  C12N1/20 ,  C12P19/04

CPC classification number: C08L1/02 ,  C12N1/20 ,  C12P19/04

Abstract: Disclosed herein is a novel gluconacetobacter strain having cellulose producing activity. Specifically, the present invention relates to a novel gluconacetobacter strain producing nano-structured cellulose in a highly efficient manner. The cellulose produced by the strain, due to its superb thermodynamic properties, can be characterized as nano-structured bacterial cellulose and therefore utilized as a bio-nano-fiber. Particularly, the cellulose can be impregnated with a resin to form a cellulose-based resin which can be effectively adapted for a substrate for a liquid crystal display (LCD).

Abstract translation: 本文公开了具有纤维素生产活性的新颖的葡萄糖酸菌属菌株。 具体地说，本发明涉及以高效的方式生产纳米结构纤维素的新颖的葡糖酸菌属菌株。 该菌株由于其极好的热力学性质而产生的纤维素可以表征为纳米结构的细菌纤维素，因此用作生物纳米纤维。 特别地，纤维素可以用树脂浸渍以形成可以有效地适用于液晶显示器（LCD）的基板的纤维素类树脂。

公开(公告)号：US07741892B2

公开(公告)日：2010-06-22

申请号：US12215456

申请日：2008-06-27

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C1/18

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.

Abstract translation: 公开了一种数据输出控制器，其包括使能信号控制器，其响应于DQ关闭信号和写入信号产生具有预定脉冲宽度的控制信号，并响应于读取信号和控制信号产生时钟使能信号 在读取信号被激活时与控制信号同步;以及时钟发生器，其在使能信号的激活周期期间接收使能信号和内部时钟信号，并与内部时钟信号同步地产生数据时钟信号。

公开(公告)号：US07554877B2

公开(公告)日：2009-06-30

申请号：US12071741

申请日：2008-02-26

Applicant: Tae-Jin Kang ,  Bong-Hwa Jeong

Inventor： Tae-Jin Kang ,  Bong-Hwa Jeong

IPC: G11C8/00

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract translation: 用于输出存储在半导体存储器件的核心中的数据的数据输出电路包括用于通过使用外部时钟产生上升时钟和下降时钟的时钟发生器，用于输出上升时钟和下降时钟的时钟转发器 响应于外部电压电平检查信号的高压时钟和低电压时钟;电平移位器，用于输出通过移位与高电压时钟同步的数据产生的高电压数据;数据载体，用于输出低电压数据 与低电压时钟同步;以及数据中继器，用于响应于外部电压电平检查信号输出高电压数据和低电压数据中的一个。

公开(公告)号：US20090154267A1

公开(公告)日：2009-06-18

申请号：US12156859

申请日：2008-06-05

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C11/00 ,  H03L7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2254 ,  H03K5/131

Abstract: A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.

Abstract translation: 描述了具有时钟信号发生电路的半导体存储器件，该时钟信号产生电路能够通过基于熔丝切断来控制上升和下降时钟信号的输出定时来控制符合PVT波动的数据输出。 时钟信号发生电路包括：熔丝单元，用于基于熔丝的熔丝切割产生第一和第二熔丝信号;控制信号产生单元，用于响应于熔丝信号产生第一和第二熔丝信号;时钟信号延迟单元， 延迟时钟信号，通过由控制信号指定的延迟部分延迟外部时钟信号;以及时钟产生单元，用于与延迟时钟信号的上升沿同步地产生第一内部时钟信号，并产生第二内部时钟信号 与延迟的时钟信号的下降沿同步。

公开(公告)号：US20090153262A1

公开(公告)日：2009-06-18

申请号：US12217203

申请日：2008-07-01

Applicant: Tae Jin Kang ,  Seung Hyun Ryu

Inventor： Tae Jin Kang ,  Seung Hyun Ryu

IPC: H01P5/12

CPC classification number: H04B1/48

Abstract: A repeater of a global input/output line includes a data transmitter including first and second drivers for outputting data signals of the global input/output line through different transmission routes in response to a transmission direction control signal, and a third driver for driving the global input/output line in response to an output signal of the data transmitter.

Abstract translation: 全局输入/输出线的中继器包括数据发射器，其包括用于响应于传输方向控制信号通过不同传输路由输出全局输入/输出线的数据信号的第一和第二驱动器，以及用于驱动全局 响应于数据发射器的输出信号的输入/输出线。

公开(公告)号：US20090115478A1

公开(公告)日：2009-05-07

申请号：US12215456

申请日：2008-06-27

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03L7/00

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.

Abstract translation: 公开了一种数据输出控制器，其包括使能信号控制器，其响应于DQ关闭信号和写入信号产生具有预定脉冲宽度的控制信号，并响应于读取信号和控制信号产生时钟使能信号 在读取信号被激活时与控制信号同步;以及时钟发生器，其在使能信号的激活周期期间接收使能信号和内部时钟信号，并与内部时钟信号同步地产生数据时钟信号。