公开(公告)号：US20080003979A1

公开(公告)日：2008-01-03

申请号：US11768674

申请日：2007-06-26

Applicant: Ki-Tae JANG ,  Yong-Joon Kim ,  Kyoung-Taek Kim ,  Yong-Tae Kim ,  Min-Sung Kim

Inventor： Ki-Tae JANG ,  Yong-Joon Kim ,  Kyoung-Taek Kim ,  Yong-Tae Kim ,  Min-Sung Kim

IPC: H04M1/66

CPC classification number: H04M1/66 ,  H04W8/183 ,  H04W8/24 ,  H04W8/245 ,  H04W12/0802 ,  H04W12/1206

Abstract: Provided is a method for tracking a lost mobile station. The method includes, when a replacement Subscriber Identity Module (SIM) card is installed, determining whether the replacement SIM card is registered as a licensed replacement SIM card; when the SIM card is not registered, transmitting a previously stored tracking short message to a preset destination; and upon receipt of a tracking response short message, setting a tracking lock mode for limiting use of some functions of the mobile station.

Abstract translation: 提供了一种跟踪丢失的移动台的方法。 该方法包括：当安装替换用户身份模块（SIM）卡时，确定替换SIM卡是否被注册为许可替换SIM卡; 当SIM卡未被注册时，将预先存储的跟踪短消息发送到预设目的地; 并且在接收到跟踪响应短消息时，设置用于限制移动台的某些功能的使用的跟踪锁定模式。

公开(公告)号：US20070184622A1

公开(公告)日：2007-08-09

申请号：US11732765

申请日：2007-04-04

Applicant: Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

Inventor： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

IPC: H01L21/336

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7835

Abstract: The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

公开(公告)号：US20070132005A1

公开(公告)日：2007-06-14

申请号：US11562223

申请日：2006-11-21

Applicant: Young-Ho Kim ,  Yong-Tae Kim ,  Weon-Ho Park ,  Kyoung-Hwan Kim ,  Ji-Hoon Park

Inventor： Young-Ho Kim ,  Yong-Tae Kim ,  Weon-Ho Park ,  Kyoung-Hwan Kim ,  Ji-Hoon Park

IPC: H01L21/336

CPC classification number: H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: An electrically erasable and programmable read only memory (EEPROM) is fabricated by forming isolation patterns defining active regions in predetermined regions of a semiconductor substrate including a memory transistor region and a selection transistor region. A gate insulating layer having tunnel regions is formed on the active regions. A first conductive layer is formed on the resultant structure having the gate insulating layer. The first conductive layer is patterned to form openings exposing top surfaces of the isolation patterns. The patterning takes place such that a distance between a selected opening and the active region adjacent the opening varies depending on the width of the isolation pattern disposed under the opening. Related EEPROM devices are also disclosed.

Abstract translation: 通过在包括存储晶体管区域和选择晶体管区域的半导体衬底的预定区域中形成限定有源区域的隔离图案来制造电可擦除和可编程只读存储器（EEPROM）。 在有源区上形成具有隧道区的栅极绝缘层。 在具有栅极绝缘层的所得结构上形成第一导电层。 图案化第一导电层以形成露出隔离图案顶表面的开口。 进行图案化，使得所选择的开口和邻近开口的有源区域之间的距离根据设置在开口下方的隔离图案的宽度而变化。 还公开了相关的EEPROM器件。

公开(公告)号：US20070019654A1

公开(公告)日：2007-01-25

申请号：US10558431

申请日：2004-05-14

Applicant: Sam-Chul Ha ,  Seung-Myun Baek ,  Koon-Seok Lee ,  Yong-Tae Kim

Inventor： Sam-Chul Ha ,  Seung-Myun Baek ,  Koon-Seok Lee ,  Yong-Tae Kim

IPC: H04J1/16 ,  H04L12/56

CPC classification number: H04L43/00 ,  H04L12/2803 ,  H04L12/2818 ,  H04L12/2825 ,  H04L43/0817 ,  H04L2012/2849

Abstract: The present invention discloses a home network system using a living network control protocol. The home network system includes: an electric device having at least two heterogeneous function means; a network based on a predetermined protocol; and a network manager for controlling and/or monitoring the electric device through the network, the electric device including a packet processing device having one node address provided by the network manager, generating a packet having the node address, transmitting the packet to the network manager, address from the network manager, and enabling the heterogeneous function means corresponding to a command included in the packet to execute the command.

Abstract translation: 本发明公开了一种使用生活网络控制协议的家庭网络系统。 家庭网络系统包括：具有至少两个异构功能装置的电子装置; 基于预定协议的网络; 以及网络管理器，用于通过网络控制和/或监视电子设备，该电子设备包括具有由网络管理器提供的一个节点地址的分组处理设备，生成具有节点地址的分组，将分组发送到网络管理器 来自网络管理器的地址，并且启用与包括在分组中的命令相对应的异构功能装置来执行命令。

公开(公告)号：US07148110B2

公开(公告)日：2006-12-12

申请号：US11415466

申请日：2006-05-01

Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

IPC: H02L21/336

CPC classification number: H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/792

Abstract: In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In addition, the local-length nitride layer is self-aligned, which prevents nitride misalignment, and therefore leads to reduced threshold voltage variation among the devices.

Abstract translation: 在本地长度的氮化物SONOS器件及其形成方法中，提供局部长度的氮化物浮栅结构，用于减轻或防止氮化物浮栅中的横向电子迁移。 该结构包括薄栅极氧化物，其导致具有较低阈值电压的器件。 此外，局部长度的氮化物层是自对准的，这防止氮化物不对准，并且因此导致器件之间的阈值电压变化降低。

公开(公告)号：US20060133174A1

公开(公告)日：2006-06-22

申请号：US11270711

申请日：2005-11-08

Applicant: Seong-Il Kim ,  Yong-Tae Kim ,  Young-Hwan Kim ,  Chun-Keun Kim ,  Min-Soo Youm

Inventor： Seong-Il Kim ,  Yong-Tae Kim ,  Young-Hwan Kim ,  Chun-Keun Kim ,  Min-Soo Youm

IPC: G11C7/00

CPC classification number: H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/1675

Abstract: Provided is a phase-change RAM containing a substrate, a lower electrode, a phase-change material, an upper electrode and a thermal dissipation layer, wherein the thermal dissipation layer contains an aluminum-nitride thermal dissipation layer having a high heat conductivity, and the lower electrode contains a titanium-nitride electrode which generates a great amount of heat generated using a small amount of current and has a low heat conductivity, whereby heat generated between the phase-change material and the electrode is not transferred to the interior of a device but fast dissipated to the exterior thereof, so as to enable a high speed operation using low current and improve reliability of the device.

Abstract translation: 提供了一种包含基板，下电极，相变材料，上电极和散热层的相变RAM，其中散热层包含具有高导热性的氮化铝散热层，以及 下电极含有氮化钛电极，其产生使用少量电流产生的大量热量并且具有低导热性，由此在相变材料和电极之间产生的热量不会转移到 器件，但是快速消散到其外部，以便能够使用低电流的高速操作并且提高器件的可靠性。

公开(公告)号：US20050245031A1

公开(公告)日：2005-11-03

申请号：US11096038

申请日：2005-03-31

Applicant: Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

Inventor： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825

Abstract: A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate. The select transistor is spaced apart from the control transistor. The select transistor, which is formed on the tunneling oxide layer, includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.

Abstract translation: 制造EEPROM单元的方法包括在半导体衬底上生长第一氧化物层; 在所述第一氧化物层上形成第一导电层; 通过对所述第一导电层和所述第一氧化物层进行构图来形成第一导电图案和隧道氧化物层，所述隧穿氧化物层设置在所述第一导电图案下方; 在所述第一导电图案和所述基板的侧壁上形成栅氧化层，并在所述第一导电图案的两侧上形成第二导电图案; 通过将所述第一导电图案电连接到所述第二导电图案来形成用于浮置栅极的导电层; 在浮栅的导电层上形成耦合氧化物层; 在所述耦合氧化物层上形成第三导电层; 以及通过图案化第三导电层，耦合氧化物层和浮栅的导电层来形成选择晶体管和控制晶体管。 选择晶体管与控制晶体管间隔开。 形成在隧道氧化物层上的选择晶体管包括由选择栅极，第一耦合氧化物图案和第一浮置栅极形成的栅极堆叠，并且控制晶体管包括由控制栅极形成的栅极堆叠， 第二耦合氧化物图案和第二浮栅。

公开(公告)号：US20050153502A1

公开(公告)日：2005-07-14

申请号：US11025279

申请日：2004-12-29

Applicant: Jae-Hwang Kim ,  Yong-Suk Choi ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Young-Sam Park

Inventor： Jae-Hwang Kim ,  Yong-Suk Choi ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Young-Sam Park

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42328

Abstract: A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

Abstract translation: 提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。 通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。 选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。 栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。 具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。 通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。 使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。

公开(公告)号：US20050133849A1

公开(公告)日：2005-06-23

申请号：US11000011

申请日：2004-12-01

Applicant: Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

Inventor： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

Abstract: A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.

Abstract translation: 具有自对准电荷捕获层的半导体存储器件及其制造方法，其中确保ONO层的一致长度。 这里，绝缘层叠结构与导电间隔物的底面自对准。

公开(公告)号：US20050003614A1

公开(公告)日：2005-01-06

申请号：US10875720

申请日：2004-06-25

Applicant: Hong-kook Min ,  Yong-tae Kim

Inventor： Hong-kook Min ,  Yong-tae Kim

IPC: H01L27/112 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/76

CPC classification number: H01L27/11521 ,  H01L27/105 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11293 ,  H01L27/11526

Abstract: A semiconductor memory device included in a system-on-chip (SOC) or a microcomputer chip. The semiconductor memory device may include a flash memory cell array unit and a mask read-only memory (ROM) cell array unit which are formed in a single memory block without an isolation layer for separating the two units. Transistors included in the flash memory unit and the mask ROM unit are the same type and may have two threshold voltages. The transistor in each memory cell unit may be a split gate transistor, a metal-oxide-nitride-oxide-silicon, or silicon-oxide-nitride-oxide-silicon transistor. Further, the transistor included in the mask ROM unit in the semiconductor memory device may include enhancement transistors or depletion transistors in which a dopant ion-implanted region is formed at channel portions.

Abstract translation: 包括在片上系统（SOC）或微计算机芯片中的半导体存储器件。 半导体存储器件可以包括闪存单元阵列单元和掩模只读存储器（ROM）单元阵列单元，其形成在没有用于分离两个单元的隔离层的单个存储器块中。 包括在闪存单元和掩模ROM单元中的晶体管是相同类型的并且可以具有两个阈值电压。 每个存储单元单元中的晶体管可以是分离栅极晶体管，金属氧化物 - 氮化物 - 氧化物 - 硅或氧化硅 - 氮化物 - 氧化物 - 硅晶体管。 此外，包括在半导体存储器件中的掩模ROM单元中的晶体管可以包括其中在沟道部分形成掺杂剂离子注入区的增强晶体管或耗尽型晶体管。