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    SOLAR CELL AND METHOD FOR MANUFACTURING SAME
    52.
    发明申请
    SOLAR CELL AND METHOD FOR MANUFACTURING SAME 审中-公开
    太阳能电池及其制造方法

    公开(公告)号：US20110139216A1

    公开(公告)日：2011-06-16

    申请号：US13058515

    申请日：2009-08-10

    Applicant: Yoo Jin Lee ,  In Goo Jang ,  Dong Jee Kim ,  Seok Pil Jang ,  Young Ho Lee ,  Byung Lee, II ,  Tack Yong Jang

    Inventor： Yoo Jin Lee ,  In Goo Jang ,  Dong Jee Kim ,  Seok Pil Jang ,  Young Ho Lee ,  Byung Lee, II ,  Tack Yong Jang

    IPC: H01L31/042 ,  H01L31/20 ,  H01L31/06

    CPC classification number: H01L31/077 ,  H01L31/0392 ,  H01L31/046 ,  Y02E10/50

    Abstract: A solar cell and a manufacturing method thereof are disclosed. The solar cell in accordance with the present invention includes a substrate 100; a lower electrode 111a formed on the substrate 100; a photoelectric element unit 200a including a polycrystalline photoelectric element 210 formed on the lower electrode 111a and formed by stacking a plurality of polycrystalline semiconductor layers 211a, 212a, and 213a, and a amorphous photoelectric element 220 formed on the polycrystalline photoelectric element 210 and formed by stacking a plurality of amorphous semiconductor layers 221, 222, and 223; and an upper electrode 400 formed on the photoelectric element unit 200a.

    Abstract translation: 公开了一种太阳能电池及其制造方法。 根据本发明的太阳能电池包括基板100; 形成在基板100上的下电极111a; 包括形成在下电极111a上并通过层叠多个多晶半导体层211a，212a和213a形成的多晶光电元件210的光电元件单元200a和形成在多晶光电元件210上的非晶光电元件220，并由 堆叠多个非晶半导体层221,222和223; 以及形成在光电元件单元200a上的上电极400。

    METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL
    53.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL 审中-公开
    制造具有应变通道的半导体器件的方法

    公开(公告)号：US20110003450A1

    公开(公告)日：2011-01-06

    申请号：US12646207

    申请日：2009-12-23

    Applicant: Young-Ho LEE ,  Tae-Hang Ahn ,  Seung-Beom Baek ,  Jun-Hee Cho ,  Jeong-Seon Kim

    Inventor： Young-Ho LEE ,  Tae-Hang Ahn ,  Seung-Beom Baek ,  Jun-Hee Cho ,  Jeong-Seon Kim

    IPC: H01L21/336

    CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/78 ,  H01L29/7848

    Abstract: A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.

    Abstract translation: 一种用于形成半导体器件的方法包括在硅衬底上形成栅极图案，在栅极图案的两个侧壁上形成栅极间隔物，在每个栅极间隔物的侧壁上形成虚拟栅极隔离物，形成具有倾斜 通过凹槽蚀刻硅衬底沿着栅极图案下方的沟道区域的方向延伸的侧壁，通过选择性外延生长工艺用成为源极区域或漏极区域的外延膜填充凹部区域， 虚拟栅极隔板。

    Adaptive image size conversion apparatus and method thereof
    54.
    发明授权
    Adaptive image size conversion apparatus and method thereof 有权
    自适应图像尺寸转换装置及其方法

    公开(公告)号：US07724983B2

    公开(公告)日：2010-05-25

    申请号：US11483623

    申请日：2006-07-11

    Applicant: Young-ho Lee

    Inventor： Young-ho Lee

    IPC: G06K9/32

    CPC classification number: G06T3/0012 ,  G06K9/00228

    Abstract: An image size conversion apparatus and an image size conversion method are provided. The image size conversion apparatus includes an area detector which detects an interested area having a certain image distinguished over a general image from an input image, a scale ratio adjustor which adjusts a scale ratio for the interested area detected by the area detector, and a scaler to perform scaling for the input image according to the adjusted scale ratio. Accordingly, the scale ratio can be adjusted according to features of the input image so that an image without distortion can be displayed on a screen.

    Abstract translation: 提供了图像尺寸转换装置和图像尺寸转换方法。 图像尺寸转换装置包括一个区域检测器，它检测一个感兴趣区域，该感兴趣区域具有一个来自输入图像的一般图像区分的特定图像;调整比例调整器，调节由该区域检测器检测到的感兴趣区域的比例;以及一个缩放器 根据调整的比例比例对输入图像执行缩放。 因此，可以根据输入图像的特征来调整比例，使得在屏幕上不显示没有失真的图像。

    METHODS OF FORMING FINE PATTERNS IN THE FABRICATION OF SEMICONDUCTOR DEVICES
    55.
    发明申请
    METHODS OF FORMING FINE PATTERNS IN THE FABRICATION OF SEMICONDUCTOR DEVICES 有权
    在半导体器件制造中形成精细图案的方法

    公开(公告)号：US20100090349A1

    公开(公告)日：2010-04-15

    申请号：US12639542

    申请日：2009-12-16

    Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

    Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

    IPC: H01L23/48

    CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

    Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

    Lens barrel assembly of camera module and laser apparatus for assembling the same
    56.
    发明授权
    Lens barrel assembly of camera module and laser apparatus for assembling the same 失效
    相机模块的镜筒组件和用于组装的激光装置

    公开(公告)号：US07663819B2

    公开(公告)日：2010-02-16

    申请号：US11905749

    申请日：2007-10-03

    Applicant: Young Ho Lee

    Inventor： Young Ho Lee

    IPC: G02B7/02 ,  G02B15/14

    CPC classification number: G02B7/021 ,  G02B9/16 ,  G02B13/001 ,  G02B13/0035

    Abstract: A lens barrel assembly of a camera module and a laser apparatus for assembling the lens barrel assembly are provided. The lens barrel assembly of a camera module includes: at least one lens; a barrel provided with a lens exposing hole having a predetermined size which is formed to penetrate a central portion of a closed upper surface of the barrel, wherein the lens is inserted from an lower opening of the barrel toward the lens exposing hole; and a stopping protrusion which is formed by fuse-securing a fused material on a boundary region between an outer circumference of the lens and an opened inner surface of the barrel by illumination of a laser beam on the opened inner surface of the barrel.

    Abstract translation: 提供了一种用于组装透镜镜筒组件的相机模块和激光装置的镜筒组件。 相机模块的镜筒组件包括：至少一个透镜; 设置有具有预定尺寸的透镜露出孔的桶，其形成为穿透所述镜筒的封闭上表面的中心部分，其中所述透镜从所述镜筒的下开口插入所述镜片曝光孔; 以及止动突起，其通过在所述筒的敞开的内表面上照射激光束来将熔融材料熔合固定在所述透镜的外周和所述镜筒的打开的内表面之间的边界区域上。

    Methods of forming fine patterns in the fabrication of semiconductor devices
    57.
    发明申请
    Methods of forming fine patterns in the fabrication of semiconductor devices 有权
    在半导体器件的制造中形成精细图案的方法

    公开(公告)号：US20090311861A1

    公开(公告)日：2009-12-17

    申请号：US12290420

    申请日：2008-10-30

    Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

    Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

    IPC: H01L21/302

    CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

    Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

    METHODS OF FORMING SEMICONDUCTOR DEVICE PATTERNS
    58.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE PATTERNS 有权
    形成半导体器件图案的方法

    公开(公告)号：US20090298276A1

    公开(公告)日：2009-12-03

    申请号：US12477468

    申请日：2009-06-03

    Applicant: Young-Ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

    Inventor： Young-Ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

    IPC: H01L21/441 ,  H01L21/467

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/1052

    Abstract: A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends. The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns. Conductive lines may be formed in the trenches.

    Abstract translation: 在半导体衬底上的蚀刻目标层上形成包括多个平行线部分的第一掩模层图案。 在第一掩模层图案和第一掩模层图案的平行线部分之间的蚀刻目标层的部分上形成牺牲层。 第二掩模层图案形成在牺牲层上，第二掩模层图案包括设置在第一掩模层图案的相邻的平行线部分之间的相应的平行线，其中第一掩模层图案和 第二掩模层图案由牺牲层分离。 形成第三掩模层图案，其包括覆盖第一掩模层图案和第二掩模层图案的线部分的相应第一和第二端的第一和第二部分，并且在第一和第二掩模层图案的线部分处具有开口 在第一和第二端之间。 使用第三掩模层图案，第一掩模层图案和第二掩模层图案作为掩模来蚀刻牺牲层和蚀刻目标层，从而在蚀刻目标层中形成多个平行的沟槽 第一和第二掩模层图案。 可以在沟槽中形成导电线。

    Printed circuit board and manufacturing method of the same
    59.
    发明申请
    Printed circuit board and manufacturing method of the same 审中-公开
    印刷电路板及其制造方法相同

    公开(公告)号：US20090133920A1

    公开(公告)日：2009-05-28

    申请号：US12216374

    申请日：2008-07-02

    Applicant: Keun-Ho Kim ,  Dek-Gin Yang ,  Yun-Seok Hwang ,  Chan-Yeup Chung ,  Young-Ho Lee ,  Cheol-Ho Heo

    Inventor： Keun-Ho Kim ,  Dek-Gin Yang ,  Yun-Seok Hwang ,  Chan-Yeup Chung ,  Young-Ho Lee ,  Cheol-Ho Heo

    IPC: H05K1/11 ,  H05K3/10

    CPC classification number: H05K3/4641 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09554 ,  Y10T29/49165

    Abstract: A printed circuit board and a manufacturing method of the same. The method includes forming a circuit board by selectively positioning a heat release layer among multiple insulation layers that have circuit patterns formed on their surfaces, perforating a through-hole that penetrates through one side and the other side of the circuit board, forming a metal film over the heat release layer exposed at an inner wall surface of the through-hole, and forming a plating layer by depositing a conductive metal over an inner wall of the through-hole. By having the heat release layer selectively inserted inside the circuit board, the heat releasing effect may be improved, and the bending strength may be increased. Moreover, a reliable electrical connection can be implemented between the heat release layer and the circuit pattern, making it possible to utilize the heat release layer as a power supply layer or a ground layer.

    Abstract translation: 一种印刷电路板及其制造方法。 该方法包括通过在其表面上形成有电路图案的多个绝缘层中选择性地定位放热层来形成电路板，穿透穿过电路板的一侧和另一侧的通孔，形成金属膜 在通孔的内壁表面露出的放热层上，通过在通孔的内壁上沉积导电金属而形成镀层。 通过使散热层选择性地插入电路板内，可以提高散热效果，并且可以提高弯曲强度。 此外，可以在散热层和电路图案之间实现可靠的电连接，使得可以将散热层用作电源层或接地层。

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