BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS
    51.
    发明申请
    BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS 有权
    用于存储阵列的非访问模式下的位线浮动

    公开(公告)号:US20110149666A1

    公开(公告)日:2011-06-23

    申请号:US12645623

    申请日:2009-12-23

    IPC分类号: G11C7/00 G11C5/14

    CPC分类号: G11C7/12 G11C5/141 G11C11/413

    摘要: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

    摘要翻译: 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如,这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中,从而如果唤醒信号不处于活动状态,则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗,例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

    BURIED BIT LINE PROCESS AND SCHEME
    52.
    发明申请

    公开(公告)号:US20110101435A1

    公开(公告)日:2011-05-05

    申请号:US12940207

    申请日:2010-11-05

    IPC分类号: H01L29/94 H01L21/334

    摘要: The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.

    摘要翻译: 该实施例提供了一种掩埋位线处理和方案。 掩埋位线设置在形成在衬底中的沟槽中。 掩埋位线包括形成在与沟槽相邻的衬底的一部分中的扩散区域。 阻挡层形成在沟槽的一部分侧壁上。 导电插塞形成在沟槽中,覆盖扩散区域和阻挡层的侧壁。

    Anti-mismating electrical connector and method for manufacting same
    53.
    发明授权
    Anti-mismating electrical connector and method for manufacting same 失效
    防错电连接器及其制造方法

    公开(公告)号:US07909659B2

    公开(公告)日:2011-03-22

    申请号:US12822191

    申请日:2010-06-24

    申请人: Yung-Chang Cheng

    发明人: Yung-Chang Cheng

    IPC分类号: H01R13/64

    摘要: An electrical connector (100) includes an insulative housing (20), a plurality of conductive contacts retained in the insulative housing, a shielding member (3) covering the insulative housing and an insulative cover (50) molded outside of the shielding member. The insulative cover has a lever portion (53) extending inside the shielding member and being sandwiched between a portion of the shielding member and the insulative housing. The insulative cover defines a slit (510) on an outer surface (51) thereof for anti-mismating. The insulative cover has a floor piece (511) located below the slit. The lever portion is connected to the floor piece for preventing the floor piece from being cracked.

    摘要翻译: 电连接器(100)包括绝缘壳体(20),保持在绝缘壳体中的多个导电触头,覆盖绝缘壳体的屏蔽构件(3)和在屏蔽构件外部模制的绝缘盖(50)。 所述绝缘罩具有在所述屏蔽部件的内部延伸并被夹在所述屏蔽部件的一部分与所述绝缘壳体之间的杆部(53)。 绝缘盖在其外表面(51)上限定了用于防错误的狭缝(510)。 绝缘盖具有位于狭缝下方的地板片(511)。 杠杆部分连接到地板件以防止地板件破裂。

    CARRIER FILM FOR MOUNTING POLISHING WORKPIECE AND METHOD FOR MAKING THE SAME
    54.
    发明申请
    CARRIER FILM FOR MOUNTING POLISHING WORKPIECE AND METHOD FOR MAKING THE SAME 有权
    用于安装抛光工具的载体膜及其制造方法

    公开(公告)号:US20110045751A1

    公开(公告)日:2011-02-24

    申请号:US12907382

    申请日:2010-10-19

    IPC分类号: B24B41/06 B32B37/12 B29C65/00

    摘要: The present invention relates to a carrier film for mounting a polishing workpiece. The carrier film comprises a surface substrate and a buffer substrate. The surface substrate consists of first elastomer, the first elastomer comprising a plurality of first holes; wherein the first holes have a drop shape, and each of the first holes has an opening. The buffer substrate consists of second elastomer, the second elastomer comprising a plurality of second holes. The surface substrate and the buffer substrate are adhered with adhesive comprising the first or the second elastomer. A method for making the carrier film is also provided. When polishing, the carrier film provides a good buffer property to conduct and release down force applied on the polishing workpiece.

    摘要翻译: 本发明涉及一种用于安装抛光工件的载体膜。 载体膜包括表面基板和缓冲基板。 所述表面基板由第一弹性体构成,所述第一弹性体包括多个第一孔; 其中所述第一孔具有液滴形状,并且每个所述第一孔具有开口。 缓冲衬底由第二弹性体组成,第二弹性体包括多个第二孔。 表面基材和缓冲基材用包含第一或第二弹性体的粘合剂粘合。 还提供了制造载体膜的方法。 当抛光时,载体膜提供良好的缓冲性能以传导和释放施加在抛光工件上的下压力。

    Polishing Pad, the Use Thereof and the Method for Manufacturing the Same
    56.
    发明申请
    Polishing Pad, the Use Thereof and the Method for Manufacturing the Same 有权
    抛光垫,其使用方法及其制造方法

    公开(公告)号:US20110000141A1

    公开(公告)日:2011-01-06

    申请号:US12883446

    申请日:2010-09-16

    IPC分类号: B24D11/00 B24D3/00

    摘要: The present invention mainly relates to a polishing pad comprising a base material comprising fibers; a first membrane with low permeability; a two-component paste formed on the upper surface of the first membrane with low permeability for adhering the base material to the first membrane with low permeability; and a polyurethane paste formed on the lower surface of the first membrane with low permeability. A method of polishing a substrate comprising using the polishing pad and a method for manufacturing the polishing pad as described above are also provided. The polishing pad as mentioned above prevents the polishing pad from detaching from the polishing platen or head. The polishing pad is easy to be replaced without leaving residues on the polishing platen or head.

    摘要翻译: 本发明主要涉及一种包括由纤维构成的基材的抛光垫; 具有低渗透性的第一膜; 在所述第一膜的上表面上形成低渗透性的双组分糊料,用于将所述基材粘附到所述第一膜,所述第一膜具有低渗透性; 以及形成在第一膜的下表面上的低渗透性的聚氨酯浆料。 还提供了一种抛光包括使用抛光垫的基板的方法和如上所述的用于制造抛光垫的方法。 如上所述的抛光垫防止抛光垫从抛光台板或头部分离。 抛光垫易于更换,而不会在研磨台板或头部上留下残留物。

    Optical connector assembly with a low profile
    58.
    再颁专利
    Optical connector assembly with a low profile 失效
    光连接器组件具有低外形

    公开(公告)号:USRE41933E1

    公开(公告)日:2010-11-16

    申请号:US11544037

    申请日:2006-10-05

    IPC分类号: G02B6/36

    CPC分类号: G02B6/3879 G02B6/3893

    摘要: An optical connector assembly (2) has two optical connectors (3) and a combiner (5). Each optical connector has a connector body (30) with an angled latching arm (4) formed on the connector body. The latching arm has a fixed end (41) on the connector body and a free distal end. A groove (430) is defined on the distal end. The combiner has a combiner body (6) holding the optical connectors and a cantilevered trigger arm (7). The trigger arm has a fixed end on the combiner body and a free distal end. A rod (72) is formed on the distal end of the trigger arm, and is received in the grooves of the optical connectors.

    摘要翻译: 光学连接器组件(2)具有两个光学连接器(3)和组合器(5)。 每个光学连接器具有连接器主体(30),其具有形成在连接器主体上的成角度的锁定臂(4)。 锁定臂在连接器主体上具有固定的端部(41)和自由的远端。 凹槽(430)限定在远端。 组合器具有保持光学连接器的组合体(6)和悬臂式触发臂(7)。 触发臂在组合器主体上具有固定端和自由远端。 杆(72)形成在触发臂的远端,并被容纳在光连接器的槽中。

    Electrical connector assembly with a FFC module
    59.
    发明授权
    Electrical connector assembly with a FFC module 失效
    带FFC模块的电气连接器组件

    公开(公告)号:US07833048B2

    公开(公告)日:2010-11-16

    申请号:US12383512

    申请日:2009-03-25

    申请人: Yung-Chang Cheng

    发明人: Yung-Chang Cheng

    IPC分类号: H01R12/24

    摘要: An electrical connector assembly comprises an insulative housing defining a receiving cavity extending inwardly from a mating face thereof and a plurality of terminal receiving passages disposed in the insulative housing and in communication with the receiving cavity. A plurality of terminals are received into the corresponding terminal receiving passages. A FFC module defines a pair of FFCs with a pair of first mating portions at one end thereof and an insulative insert having a lower half section disposed between the pair of first mating portions. The FFC module has an inserting portion received into the receiving cavity of the insulative housing.

    摘要翻译: 电连接器组件包括绝缘壳体,其限定从其配合面向内延伸的接收腔和设置在绝缘壳体中并与接收腔连通的多个端子接收通道。 多个终端被接收到相应的终端接收通道中。 FFC模块限定一对FFC,其一端具有一对第一配合部分,并且绝缘插入件具有设置在该对第一配合部分之间的下半部分。 FFC模块具有插入到绝缘壳体的容纳腔中的插入部分。

    Polishing material having polishing particles and method for making the same
    60.
    发明授权
    Polishing material having polishing particles and method for making the same 有权
    具有抛光颗粒的抛光材料及其制造方法

    公开(公告)号:US07824249B2

    公开(公告)日:2010-11-02

    申请号:US11702217

    申请日:2007-02-05

    IPC分类号: B24D15/00 B24D11/00 B24B1/00

    CPC分类号: B24B37/26 B24D11/001

    摘要: The present invention relates to a polishing material having polishing particles and a method for making the same. The polishing material having polishing particles includes a base material, a plurality of polishing particles and a polymer elastic body. The base material has a plurality of fibers for defining a plurality of grid-spaces. The polishing particles are distributed in the grid-spaces. The polymer elastic body covers the base material and the polishing particles, whereby, the polishing particles are uniformly distributed on a surface of a polishing workpiece during the polishing process. Furthermore, the base material prevents the polishing particles from contacting the polishing workpiece so as to avoid scratching of the polishing workpiece. Also, the base material provides effects for sweeping the small grinded pieces.

    摘要翻译: 本发明涉及具有抛光颗粒的抛光材料及其制造方法。 具有抛光颗粒的抛光材料包括基材,多个抛光颗粒和聚合物弹性体。 基材具有用于限定多个网格空间的多根纤维。 抛光颗粒分布在网格空间中。 聚合物弹性体覆盖基材和抛光颗粒,由此在抛光过程中抛光颗粒均匀地分布在抛光工件的表面上。 此外,基材防止抛光颗粒接触抛光工件,以避免抛光工件的刮擦。 此外,基材提供了用于扫掠小磨碎片的效果。