Interface emulator using FIFOs
    51.
    发明授权

    公开(公告)号:US10049073B2

    公开(公告)日:2018-08-14

    申请号:US15621265

    申请日:2017-06-13

    Applicant: Apple Inc.

    Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

    Touch, pen and force sensor operation with variable refresh displays

    公开(公告)号:US09880649B2

    公开(公告)日:2018-01-30

    申请号:US14500653

    申请日:2014-09-29

    Applicant: Apple Inc.

    Abstract: Synchronization of display functions and various touch, stylus and/or force sensing functions for devices including a variable refresh rate (VRR) display is disclosed. In some examples, touch, stylus and/or force sensing functions can be synchronized with display frames and a display refresh rate can be adjusted by extended blanking of the display for one or more display frames. In other examples, touch, stylus and/or force sensing functions can be synchronized with display sub-frames and a display refresh rate can be adjusted by extended blanking of the display for one or more display sub-frames. Pre-warning synchronization signals can be generated to prepare one or more scan controllers to implement the appropriate scan events during and after extended blanking periods. Latency between the scan results and the corresponding image on the display can be corrected in software and/or firmware by time-stamping scan results or by dropping scan results from uncompleted scans.

    Interface Emulator using FIFOs
    54.
    发明申请

    公开(公告)号:US20170277648A1

    公开(公告)日:2017-09-28

    申请号:US15621265

    申请日:2017-06-13

    Applicant: Apple Inc.

    Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

    Variable frame refresh rate
    56.
    发明授权
    Variable frame refresh rate 有权
    可变帧刷新率

    公开(公告)号:US09495926B2

    公开(公告)日:2016-11-15

    申请号:US14557001

    申请日:2014-12-01

    Applicant: Apple Inc.

    Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.

    Abstract translation: 用于防止显示器的显示面板上的电荷累积的系统,装置和方法。 显示管道被配置为使用可变帧刷新率驱动显示器。 显示器也可以由极性反转节奏驱动,以在背对背框上交替显示面板上的极性。 在某些情况下,如果在包含用于处理相应帧的配置数据的帧分组中指定的帧刷新率节奏可以在切换到第一帧刷新率之前以奇数帧显示在显示面板上的电荷累积 第二帧刷新率。 因此,在这些情况下,显示管线可以覆盖给定帧的帧刷新率设置,以使得以第一帧刷新率显示偶数帧。

    VARIABLE FRAME REFRESH RATE
    57.
    发明申请
    VARIABLE FRAME REFRESH RATE 有权
    可变框架刷新率

    公开(公告)号:US20160155399A1

    公开(公告)日:2016-06-02

    申请号:US14557001

    申请日:2014-12-01

    Applicant: Apple Inc.

    Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.

    Abstract translation: 用于防止显示器的显示面板上的电荷累积的系统,装置和方法。 显示管道被配置为使用可变帧刷新率驱动显示器。 显示器也可以由极性反转节奏驱动,以在背对背框上交替显示面板上的极性。 在某些情况下,如果在包含用于处理对应帧的配置数据的帧分组中指定的帧刷新率节奏可以在切换到第一帧刷新率之前以奇数帧显示在显示面板上的电荷累积 第二帧刷新率。 因此,在这些情况下,显示管线可以覆盖给定帧的帧刷新率设置,以使得以第一帧刷新率显示偶数帧。

    Always-On Processor as a Coprocessor
    58.
    发明申请
    Always-On Processor as a Coprocessor 审中-公开
    始终处理器作为协处理器

    公开(公告)号:US20150362980A1

    公开(公告)日:2015-12-17

    申请号:US14305835

    申请日:2014-06-16

    Applicant: Apple Inc.

    Inventor: Brijesh Tripathi

    Abstract: A system on a chip (SOC) may include a component that remains powered when the remainder of the SOC is powered off. The component may be configured to power up other components of the SOC while keeping the central processing unit (CPU) processors powered down, in order to perform a task assigned to such other component(s). The always-on component may further include a processor, in some embodiments, which may interact with the other components to perform the task. In an embodiment, the processor within the always-on component may execute operating system (OS) software to interact with the other components while the CPU processors are powered down.

    Abstract translation: 芯片上的系统(SOC)可以包括当SOC的剩余部分断电时保持供电的组件。 该组件可以被配置为在保持中央处理单元(CPU)处理器断电的同时为SOC的其他组件供电,以便执行分配给这样的其他组件的任务。 始终在线的组件还可以包括在一些实施例中可以与其他组件交互以执行任务的处理器。 在一个实施例中,始终打开组件中的处理器可以执行操作系统(OS)软件以在CPU处理器断电时与其他组件交互。

    Interface Emulator using FIFOs
    59.
    发明申请
    Interface Emulator using FIFOs 有权
    使用FIFO的接口仿真器

    公开(公告)号:US20150356050A1

    公开(公告)日:2015-12-10

    申请号:US14459731

    申请日:2014-08-14

    Applicant: Apple Inc.

    Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

    Abstract translation: 公开了一种用于IC的接口仿真器。 接口仿真器包括第一先入先出存储器(FIFO)和第二FIFO。 第一FIFO被耦合以从接入端口接收数据,并且第二FIFO被耦合以从IC中的至少一个功能单元接收数据。 访问端口可以耦合到IC外部的设备。 外部设备可以将信息写入第一FIFO,并且该信息随后可以由IC中的功能单元读取。 类似地,功能单元可以将信息写入第二FIFO,随后外部设备读取信息。 可以根据预定义的协议将信息写入FIFO。 因此,即使在IC中没有实现用于该接口的物理连接和支持电路,也可以模拟特定类型的接口。

    MID-FRAME BLANKING
    60.
    发明申请
    MID-FRAME BLANKING 审中-公开
    中框布局

    公开(公告)号:US20150355762A1

    公开(公告)日:2015-12-10

    申请号:US14296105

    申请日:2014-06-04

    Applicant: Apple Inc.

    Abstract: Systems, apparatuses, and methods for performing mid-frame blanking. A first portion of a frame is driven to a display and then a first mid-frame blanking interval is generated. Following this first mid-frame blanking interval, a second portion of the frame is driven to the display, followed by a second mid-frame blanking interval, followed by a third portion of the frame, and so on. Any number of mid-frame blanking intervals may be introduced in a given frame. During each mid-frame blanking interval, touch sensing is performed to detect touch events on the screen for in-cell touch type displays. For displays with touch sensors electrically separated from the display common voltage layer, special sense scan steps are performed during mid-frame blanking intervals. By performing touch sensing or special sense scan steps during a frame rather than only at the end of a frame, the performance of touch sensing is improved.

    Abstract translation: 执行中帧消隐的系统,设备和方法。 帧的第一部分被驱动到显示器,然后产生第一中间帧消隐间隔。 在该第一中间帧消隐间隔之后,帧的第二部分被驱动到显示器,随后是第二中间帧消隐间隔,随后是帧的第三部分,等等。 可以在给定的帧中引入任何数量的中帧消隐间隔。 在每个中间帧消隐间隔期间,执行触摸感测以检测用于小区内触摸式显示的屏幕上的触摸事件。 对于具有与显示器公共电压层电气分离的触摸传感器的显示器,在中帧消隐间隔期间执行特殊感测扫描步骤。 通过在帧期间执行触摸感测或特殊感测扫描步骤,而不仅仅是在帧的结尾处,提高了触摸感测的性能。

Patent Agency Ranking