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    Interrupt timestamping
    2.
    发明授权
    Interrupt timestamping 有权
    中断时间戳

    公开(公告)号：US09201821B2

    公开(公告)日：2015-12-01

    申请号：US13629509

    申请日：2012-09-27

    Applicant: Apple Inc.

    Inventor： Erik P. Machnicki ,  Josh P. de Cesare ,  Manu Gulati

    IPC: G06F13/24

    CPC classification number: G06F13/24

    Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.

    Abstract translation: 一种用于保持精确中断时间戳的系统和方法。 半导体芯片包括具有多个中断源的接口的中断控制器（IC）。 响应于接收到中断，IC复制并记录存储在用于维持全局经过时间的主时基计数器中的值。 IC向对应的处理器发送中断指示。 中断服务程序（ISR）或设备驱动程序请求与中断相关联的时间戳。 处理器不是向操作系统发送请求以获得存储在主时基计数器中的当前值，而是从IC请求记录的时间戳。 IC识别与中断相关联的存储时间戳，并将其返回给处理器。

    Persistent Relocatable Reset Vector for Processor
    3.
    发明申请
    Persistent Relocatable Reset Vector for Processor 有权
    处理器持续可重定位复位向量

    公开(公告)号：US20140215182A1

    公开(公告)日：2014-07-31

    申请号：US13750013

    申请日：2013-01-25

    Applicant: APPLE INC.

    Inventor： Josh P. de Cesare ,  Gerard R. Williams, III ,  Michael J. Smith ,  Wei-Han Lien

    IPC: G06F9/30

    CPC classification number: G06F9/322 ,  G06F9/30076

    Abstract: In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.

    Abstract translation: 在一个实施例中，集成电路包括至少一个处理器。 处理器可以包括被配置为存储处理器的复位向量地址的复位向量基地址寄存器。 响应于复位，处理器可以被配置为捕获输入上的复位向量地址，更新复位向量基地址寄存器。 当复位释放时，处理器可以在复位向量地址处启动指令执行。 集成电路还可以包括耦合以提供复位向量地址的逻辑电路。 逻辑电路可以包括可用复位向量地址编程的寄存器。 更具体地，在一个实施例中，寄存器可以通过由处理器发出的写入操作来编程（例如，存储器映射的写入操作）。 因此，复位矢量地址可以在集成电路中可编程，并且可以不时地改变。

    Control of a computer system in a power-down state
    4.
    发明授权
    Control of a computer system in a power-down state 有权

    公开(公告)号：US11481019B1

    公开(公告)日：2022-10-25

    申请号：US16994372

    申请日：2020-08-14

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Josh P. de Cesare

    IPC: G06F1/3287 ,  G06F1/26 ,  G06F9/4401 ,  G06F3/06 ,  G06F11/20

    Abstract: Techniques are disclosed relating a computer system in a power-down state receiving a communication from a remote computer system and performing a task indicated by the communication. The computer system in a power-down state performs the task without transitioning from the power-down state into a power-up state. Exemplary tasks performed in the power-down state include uploading one or more files to a remote computer system, downloading one or more files from a remote computer system, deleting one or more files from the computer system, accessing input/output devices, disabling the computer system, and performing a memory check on the computer system.

    Control of a computer system in a power-down state
    5.
    发明授权
    Control of a computer system in a power-down state 有权

    公开(公告)号：US10747295B1

    公开(公告)日：2020-08-18

    申请号：US15721411

    申请日：2017-09-29

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Josh P. de Cesare

    IPC: G06F1/3287 ,  G06F1/26 ,  G06F9/4401 ,  G06F3/06 ,  G06F11/20

    Abstract: Techniques are disclosed relating a computer system in a power-down state receiving a communication from a remote computer system and performing a task indicated by the communication. The computer system in a power-down state performs the task without transitioning from the power-down state into a power-up state. Exemplary tasks performed in the power-down state include uploading one or more files to a remote computer system, downloading one or more files from a remote computer system, deleting one or more files from the computer system, accessing input/output devices, disabling the computer system, and performing a memory check on the computer system.

    Secure data access between computing devices using host-specific key
    6.
    发明授权
    Secure data access between computing devices using host-specific key 有权

    公开(公告)号：US10558589B1

    公开(公告)日：2020-02-11

    申请号：US15721636

    申请日：2017-09-29

    Applicant: Apple Inc.

    Inventor： Josh P. de Cesare ,  Wade Benson ,  Fabrice L. Gautier ,  Kaiehu Kaahaaina

    IPC: G06F12/14 ,  G06F21/62 ,  G06F21/60

    Abstract: Techniques are disclosed concerning secure access to data in a computing device. In one embodiment, a computing device includes a communication interface, a memory, a memory controller, and a security processor. The communication interface may communicate with a different computing device. The security processor may generate a host key in response to a successful authentication of the different computing device, and then encrypt a memory key using the host key. The security processor may also send the encrypted memory key to the memory controller, and send the host key to the different computing device. The host key may be included by the different computing device in a subsequent memory request to access data in the memory. The memory controller may, in response to the subsequent memory request, use the included host key to decrypt the encrypted memory key and use the decrypted memory key to access the data.

    Security enclave processor power control
    7.
    发明授权
    Security enclave processor power control 有权
    安全飞地处理器电源控制

    公开(公告)号：US09043632B2

    公开(公告)日：2015-05-26

    申请号：US13626522

    申请日：2012-09-25

    Applicant: Apple Inc.

    Inventor： Erik P. Machnicki ,  Manu Gulati ,  Josh P. de Cesare

    IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F7/04 ,  H04N7/16 ,  G06F11/00 ,  G06F21/57 ,  G06F21/74 ,  G06F21/70 ,  G06F21/60 ,  G06F21/71

    CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/575 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/74

    Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

    Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包裹密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

    Hardware automatic performance state transitions in system on processor sleep and wake events
    8.
    发明授权
    Hardware automatic performance state transitions in system on processor sleep and wake events 有权
    系统中处理器睡眠和唤醒事件的硬件自动性能状态转换

    公开(公告)号：US08959369B2

    公开(公告)日：2015-02-17

    申请号：US14149922

    申请日：2014-01-08

    Applicant: Apple Inc.

    Inventor： Josh P. de Cesare ,  Jung Wook Cho ,  Toshinari Takayanagi ,  Timothy J. Millet

    IPC: G06F1/00 ,  G06F1/32 ,  G09G3/18 ,  G11C5/14 ,  H04M1/00 ,  G06F1/26

    CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

    Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

    Audio accessibility assistance
    10.
    发明授权
    Audio accessibility assistance 有权

    公开(公告)号：US11200303B2

    公开(公告)日：2021-12-14

    申请号：US16144922

    申请日：2018-09-27

    Applicant: Apple Inc.

    Inventor： Gregory F. Hughes ,  Anthony J. Chivetta ,  Brett D. George ,  Josh P. de Cesare ,  Santo S. Sapienza ,  Ion Valentin Pistol

    IPC: G06F21/32 ,  G06F21/84 ,  G06F21/57 ,  G10L13/00 ,  G06F21/31

    Abstract: Techniques are disclosed relating to providing audio prompts. In one embodiment, a computing device includes a display, an audio circuit coupled to a speaker, first and second processors, and memory. The memory has first program instructions executable by the first processor to provide, via a first operating system of the computing device, a visual prompt to the display to cause the display to present the visual prompt to a user and send, to the second processor, a request to provide an audio prompt corresponding to the visual prompt via the speaker to the user. The computing device also includes memory having second program instructions executable by the second processor to, in response to the request, provide, via a second operating system, an instruction to the audio circuit to play the audio prompt via the speaker.

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