Abstract:
A plane display with a foldable support. The plane display comprises a base and a back plane mounted on a plane display panel. The back plane pivots on the base by a sleeve. The connecting rod is disposed in the sleeve, and slides between a first position and a second position. An L-shaped member is fixed on the connecting rod. When the connecting rod is in the first position, the L-shaped member secures the back plane to the base at a first angle. When the connecting rod is in the second position, the L-shaped member releases the back plane from the base, and the back plane rotates with respect to the base to a second angle.
Abstract:
A transparent spherical toy includes upper and lower shell halves. The upper shell half has a bottom end face, a thickness reduced rim portion extending downwardly from the bottom end face, an outer recess formed outside of the inner space and extending upwardly from the bottom end face, and a male thread formed on the rim portion. The lower shell half has a top end face, an inner wall, a ring-shaped shoulder projecting into the inner space from the inner wall adjacent to the top end face so that the rim portion is seated against the shoulder, a female thread formed on the inner wall between the top end face and the shoulder and engaging the male thread, and a notch formed in the top end face above the female thread and aligned with the outer recess. The transparent spherical toy further includes a sealing ring disposed between the shoulder and the rim portion for providing sealing therebetween when the male and female threads engage each other tightly, and a dog mounted rotatably in the outer recess and extending therefrom into the notch for preventing the upper shell half from rotating relative to the lower shell half.
Abstract:
A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.
Abstract:
A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.
Abstract:
A metal-air fuel cell module includes a cap seat connected detachably to a casing and having a plug portion extending into an inner accommodating space in the casing for plugging an opening in the casing; a conductive gas-diffusion sheet disposed in the casing for covering sealingly air inlets in the casing, and permitting air to pass through; an electrolyte solution filled in the inner accommodating space; a metal sheet disposed in the inner accommodating space and connected detachably to the plug portion of the cap seat; a first electrode plate mounted on the casing, extending into the inner accommodating space and in electrical contact with the gas-diffusion sheet; and a second electrode plate mounted in the cap seat, extending into the inner accommodating space and in electrical contact with the metal sheet.
Abstract:
A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.
Abstract:
A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result.
Abstract:
A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.
Abstract:
A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.
Abstract:
A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.