公开(公告)号：US08392132B2

公开(公告)日：2013-03-05

申请号：US12851547

申请日：2010-08-05

申请人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G06F19/00

CPC分类号： G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

摘要： A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

摘要翻译： 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US20110270555A1

公开(公告)日：2011-11-03

申请号：US12851547

申请日：2010-08-05

申请人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G06F19/00 ,  G01R19/00

CPC分类号： G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

摘要： A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

摘要翻译： 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US08300449B2

公开(公告)日：2012-10-30

申请号：US12955657

申请日：2010-11-29

申请人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

发明人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79

摘要： A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

摘要翻译： 提供了一种电阻随机存取存储器（RRAM）及其验证方法。 RRAM包括至少一个电阻存储单元。 电阻存储单元包括电阻存储器元件和晶体管，其中电阻存储器元件的一个端子耦合到晶体管的第一端子。 验证方法包括以下步骤：确定电阻式存储单元是否通过验证。 在第一时间段期间，并且在电阻性存储器单元不能通过验证的情况下，将参考电压施加到电阻性存储元件的另一个端子，并且根据电压将电压脉冲施加到晶体管的第二端子 信号向电阻存储单元写入反向电压。

公开(公告)号：US20120075908A1

公开(公告)日：2012-03-29

申请号：US12955657

申请日：2010-11-29

申请人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

发明人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

IPC分类号： G11C11/21

CPC分类号： G11C13/0064 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79

摘要： A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

摘要翻译： 提供了一种电阻随机存取存储器（RRAM）及其验证方法。 RRAM包括至少一个电阻存储单元。 电阻存储单元包括电阻存储器元件和晶体管，其中电阻存储器元件的一个端子耦合到晶体管的第一端子。 验证方法包括以下步骤：确定电阻式存储单元是否通过验证。 在第一时间段期间，并且在电阻性存储器单元不能通过验证的情况下，将参考电压施加到电阻性存储元件的另一个端子，并且根据电压将电压脉冲施加到晶体管的第二端子 信号向电阻存储单元写入反向电压。

公开(公告)号：US20110122684A1

公开(公告)日：2011-05-26

申请号：US12650544

申请日：2009-12-31

申请人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C7/00 ,  G11C11/00 ,  G11C5/14

CPC分类号： G11C11/5678 ,  G11C7/14 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2211/5634

摘要： A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

摘要翻译： 提供电压补偿电路，具有该电压补偿电路的多电平存储器件以及用于读取多电平存储器件的电压补偿方法。 当读取存储单元时，根据参考单元的漂移电阻的特性的变化来调整施加到存储器件的参考电压。 参考电压的增加值（即电压差）对应于由漂移条件引起的电阻变化。 漂移补偿机构适应于存储器件的读取驱动器的补偿电路，其可以补偿当从存储器单元读取数据时电压电平的变化。 当发生电阻漂移时，计算漂移量并将其加到参考电压上，以避免当读出存储的数据时由电阻漂移引起的判断误差。

公开(公告)号：US08040723B2

公开(公告)日：2011-10-18

申请号：US12650544

申请日：2009-12-31

申请人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C7/00

CPC分类号： G11C11/5678 ,  G11C7/14 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2211/5634

摘要： A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

摘要翻译： 提供电压补偿电路，具有该电压补偿电路的多电平存储器件以及用于读取多电平存储器件的电压补偿方法。 当读取存储单元时，根据参考单元的漂移电阻的特性的变化来调整施加到存储器件的参考电压。 参考电压的增加值（即电压差）对应于由漂移条件引起的电阻变化。 漂移补偿机构适应于存储器件的读取驱动器的补偿电路，其可以补偿当从存储器单元读取数据时电压电平的变化。 当发生电阻漂移时，计算漂移量并将其加到参考电压上，以避免当读出存储的数据时由电阻漂移引起的判断误差。

公开(公告)号：US07885109B2

公开(公告)日：2011-02-08

申请号：US12273414

申请日：2008-11-18

申请人： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

发明人： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC分类号： G11C11/04

CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2207/2227 ,  G11C2213/79

摘要： Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.

摘要翻译： 具有低功耗的存储器和用于抑制存储器的电流泄漏的方法。 存储器的存储单元具有串联耦合的存储元件和晶体管。 当存储器未被访问时，本发明将跨越晶体管的电压设置为零。

公开(公告)号：USRE45189E1

公开(公告)日：2014-10-14

申请号：US13571798

申请日：2012-08-10

申请人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

发明人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

摘要： An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.

摘要翻译： 公开了一种基于本申请的相变存储器的写入系统的实施例。 该写入系统包括第一相变存储器（PCM）单元，第二PCM单元，第一写入电路和验证电路。 第一写入电路执行写入过程，将第一数据接收并写入第一PCM单元。 验证电路执行验证过程，并且电路还包括处理单元和第二写入电路。 处理单元读取并比较存储在第二PCM单元中的数据与第二数据。 当存储在第二PCM单元中的数据和第二数据不匹配时，第二写入电路将第二数据写入第二PCM单元。

公开(公告)号：US08031515B2

公开(公告)日：2011-10-04

申请号：US12275223

申请日：2008-11-21

申请人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

发明人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

摘要翻译： 提供了一种用于将写入数据存储到存储单元中的数据编程电路。 数据编程电路包括控制电路和电流产生电路。 控制电路根据写入数据生成控制信号。 电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。 写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

公开(公告)号：US20090135645A1

公开(公告)日：2009-05-28

申请号：US12275223

申请日：2008-11-21

申请人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

发明人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC分类号： G11C7/00 ,  G11C11/56

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

摘要翻译： 提供了一种用于将写入数据存储到存储单元中的数据编程电路。 数据编程电路包括控制电路和电流产生电路。 控制电路根据写入数据生成控制信号。 电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。 写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。