公开(公告)号：US20130114325A1

公开(公告)日：2013-05-09

申请号：US13332402

申请日：2011-12-21

申请人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

发明人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C14/009

摘要： A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

摘要翻译： 提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。 第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。 第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。 第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。 第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。 开关的第二端子耦合到第三电压。

公开(公告)号：US08392132B2

公开(公告)日：2013-03-05

申请号：US12851547

申请日：2010-08-05

申请人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G06F19/00

CPC分类号： G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

摘要： A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

摘要翻译： 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US20110122684A1

公开(公告)日：2011-05-26

申请号：US12650544

申请日：2009-12-31

申请人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C7/00 ,  G11C11/00 ,  G11C5/14

CPC分类号： G11C11/5678 ,  G11C7/14 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2211/5634

摘要： A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

摘要翻译： 提供电压补偿电路，具有该电压补偿电路的多电平存储器件以及用于读取多电平存储器件的电压补偿方法。 当读取存储单元时，根据参考单元的漂移电阻的特性的变化来调整施加到存储器件的参考电压。 参考电压的增加值（即电压差）对应于由漂移条件引起的电阻变化。 漂移补偿机构适应于存储器件的读取驱动器的补偿电路，其可以补偿当从存储器单元读取数据时电压电平的变化。 当发生电阻漂移时，计算漂移量并将其加到参考电压上，以避免当读出存储的数据时由电阻漂移引起的判断误差。

公开(公告)号：US08625361B2

公开(公告)日：2014-01-07

申请号：US13345740

申请日：2012-01-08

申请人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C7/10 ,  G11C8/16

CPC分类号： G11C8/16 ,  G11C7/14 ,  G11C8/08 ,  G11C8/18 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

摘要： A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.

摘要翻译： 提供了用于控制非易失性存储器的写入定时的电路和方法。 该方法包括以下步骤。 首先，监视执行写入操作的非易失性存储器中的至少一个存储单元的电阻状态切换，以输出控制信号。 存储单元存储具有不同电阻状态的数据状态。 通过定时控制线将写时序输入到存储单元。 接下来，基于时钟信号和控制信号来生成写入定时。 写时序在时钟信号的周期开始时被使能，并且当存储器单元完成电阻状态切换时被禁止。

公开(公告)号：US08422295B1

公开(公告)日：2013-04-16

申请号：US13332402

申请日：2011-12-21

申请人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

发明人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC分类号： G11C14/00

CPC分类号： G11C14/009

摘要： A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

摘要翻译： 提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。 第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。 第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。 第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。 第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。 开关的第二端子耦合到第三电压。

公开(公告)号：US20110270555A1

公开(公告)日：2011-11-03

申请号：US12851547

申请日：2010-08-05

申请人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G06F19/00 ,  G01R19/00

CPC分类号： G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

摘要： A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

摘要翻译： 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US08040723B2

公开(公告)日：2011-10-18

申请号：US12650544

申请日：2009-12-31

申请人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C7/00

CPC分类号： G11C11/5678 ,  G11C7/14 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2211/5634

摘要： A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

摘要翻译： 提供电压补偿电路，具有该电压补偿电路的多电平存储器件以及用于读取多电平存储器件的电压补偿方法。 当读取存储单元时，根据参考单元的漂移电阻的特性的变化来调整施加到存储器件的参考电压。 参考电压的增加值（即电压差）对应于由漂移条件引起的电阻变化。 漂移补偿机构适应于存储器件的读取驱动器的补偿电路，其可以补偿当从存储器单元读取数据时电压电平的变化。 当发生电阻漂移时，计算漂移量并将其加到参考电压上，以避免当读出存储的数据时由电阻漂移引起的判断误差。

公开(公告)号：US20130121058A1

公开(公告)日：2013-05-16

申请号：US13345740

申请日：2012-01-08

申请人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C11/00

CPC分类号： G11C8/16 ,  G11C7/14 ,  G11C8/08 ,  G11C8/18 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

摘要： A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.

摘要翻译： 提供了用于控制非易失性存储器的写入定时的电路和方法。 该方法包括以下步骤。 首先，监视执行写入操作的非易失性存储器中的至少一个存储单元的电阻状态切换，以输出控制信号。 存储单元存储具有不同电阻状态的数据状态。 通过定时控制线将写时序输入到存储单元。 接下来，基于时钟信号和控制信号来生成写入定时。 写时序在时钟信号的周期开始时被使能，并且当存储器单元完成电阻状态切换时被禁止。

公开(公告)号：US08300449B2

公开(公告)日：2012-10-30

申请号：US12955657

申请日：2010-11-29

申请人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

发明人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79

摘要： A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

摘要翻译： 提供了一种电阻随机存取存储器（RRAM）及其验证方法。 RRAM包括至少一个电阻存储单元。 电阻存储单元包括电阻存储器元件和晶体管，其中电阻存储器元件的一个端子耦合到晶体管的第一端子。 验证方法包括以下步骤：确定电阻式存储单元是否通过验证。 在第一时间段期间，并且在电阻性存储器单元不能通过验证的情况下，将参考电压施加到电阻性存储元件的另一个端子，并且根据电压将电压脉冲施加到晶体管的第二端子 信号向电阻存储单元写入反向电压。

公开(公告)号：US20120075908A1

公开(公告)日：2012-03-29

申请号：US12955657

申请日：2010-11-29

申请人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

发明人： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

IPC分类号： G11C11/21

CPC分类号： G11C13/0064 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79

摘要： A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

摘要翻译： 提供了一种电阻随机存取存储器（RRAM）及其验证方法。 RRAM包括至少一个电阻存储单元。 电阻存储单元包括电阻存储器元件和晶体管，其中电阻存储器元件的一个端子耦合到晶体管的第一端子。 验证方法包括以下步骤：确定电阻式存储单元是否通过验证。 在第一时间段期间，并且在电阻性存储器单元不能通过验证的情况下，将参考电压施加到电阻性存储元件的另一个端子，并且根据电压将电压脉冲施加到晶体管的第二端子 信号向电阻存储单元写入反向电压。