公开(公告)号：US08395922B2

公开(公告)日：2013-03-12

申请号：US13035134

申请日：2011-02-25

申请人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

发明人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  G11C16/0483 ,  G11C16/26

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。 存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。 第一读出放大器电路连接到多个第一互连。 第二读出放大器电路连接到多个第二互连。 互连上表面的高度相等。 沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小 并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

公开(公告)号：US08327229B2

公开(公告)日：2012-12-04

申请号：US12818709

申请日：2010-06-18

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： G11C29/00

CPC分类号： G11C16/3427 ,  G06F11/1068 ,  G11C7/1006 ,  G11C8/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C19/00 ,  G11C29/00

摘要： A data memory system is provided which includes a nonvolatile memory cell array, an error correction code generation circuit, an error correction code decoding circuit, and a first circuit. The nonvolatile memory cell array includes a plurality of memory cells which store digital data each having at least a value of “1” or “0” as a charge of a charge accumulation layer included in each memory cell, and use a difference between charges of the accumulation layer as a writing bit or an erasing bit. The nonvolatile memory cell array erases memory cells in units of pages, each page being formed of adjacent memory cells included in the plurality of memory cells.

摘要翻译： 提供一种包括非易失性存储单元阵列，纠错码产生电路，纠错码解码电路和第一电路的数据存储系统。 非易失性存储单元阵列包括多个存储单元，其存储每个具有至少1或0值的数字数据作为每个存储单元中包含的电荷累积层的电荷，并且使用积累层的电荷之间的差作为 写位或擦除位。 非易失性存储单元阵列以页为单位擦除存储单元，每页由包含在多个存储单元中的相邻存储单元形成。

公开(公告)号：US08185802B2

公开(公告)日：2012-05-22

申请号：US12369889

申请日：2009-02-12

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： G11C29/00

CPC分类号： G11C16/3427 ,  G06F11/1068 ,  G11C7/1006 ,  G11C8/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C19/00 ,  G11C29/00

摘要： A data memory system includes a nonvolatile memory cell array which includes a plurality of memory cells, a page adjacently formed by the plurality of memory cells being collectively erased in the nonvolatile memory cell, at least binary pieces of digital data of “1” and “0” being stored as charges of a charge accumulation layer in the memory cell, a programming bit and an erasing bit being formed by a difference between the charges of the charge accumulation layer. And the system includes an error correcting code generation circuit, an error correcting code decoding circuit, and a code conversion circuit.

摘要翻译： 一种数据存储器系统包括：非易失性存储单元阵列，其包括多个存储单元，由所述多个存储器单元相邻形成的页面在所述非易失性存储单元中被共同擦除;至少二进制数字数据“1”和“ 0“作为电荷累积层的电荷存储在存储单元中，由电荷累积层的电荷之间的差异形成的编程位和擦除位。 该系统包括纠错码产生电路，纠错码解码电路和代码转换电路。

公开(公告)号：US20120037973A1

公开(公告)日：2012-02-16

申请号：US13281083

申请日：2011-10-25

申请人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

发明人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

摘要翻译： 存储单元包括浮置栅电极，第一电极间绝缘膜和控制栅电极。 外围晶体管包括下电极，第二电极间绝缘膜和上电极。 下电极和上电极通过设置在第二电极间绝缘膜上的开口电连接。 第一和第二电极间绝缘膜包括高电容率材料，第一电极间绝缘膜具有第一结构，第二电极间绝缘膜具有与第一结构不同的第二结构。

公开(公告)号：US20120012909A1

公开(公告)日：2012-01-19

申请号：US13241965

申请日：2011-09-23

申请人： Mitsuhiro Noguchi ,  Kenji Gomikawa

发明人： Mitsuhiro Noguchi ,  Kenji Gomikawa

IPC分类号： H01L27/115

CPC分类号： G11C16/24 ,  G11C16/30 ,  H01L27/0207 ,  H01L27/0222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

摘要翻译： 半导体器件包括MOS晶体管，电容器元件，电压产生电路，接触插头和存储单元。 MOS晶体管和电容器元件分别形成在第一元件区域和第二元件区域中。 在电压产生电路中，MOS晶体管的电流路径串联连接，并且电容器元件连接到MOS晶体管的源极或漏极。 接触插塞形成在源极或漏极上，以连接MOS晶体管或MOS晶体管之一以及电容器元件之一。 位于串联连接的最后级的MOS晶体管的栅极和接触插塞之间的距离大于串联连接中位于初始阶段的第二个MOS晶体管的距离。

公开(公告)号：US08049259B2

公开(公告)日：2011-11-01

申请号：US12966115

申请日：2010-12-13

申请人： Mitsuhiro Noguchi ,  Kenji Gomikawa

发明人： Mitsuhiro Noguchi ,  Kenji Gomikawa

IPC分类号： H01L29/76 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119 ,  H01L31/113

CPC分类号： G11C16/24 ,  G11C16/30 ,  H01L27/0207 ,  H01L27/0222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

摘要翻译： 半导体器件包括MOS晶体管，电容器元件，电压产生电路，接触插头和存储单元。 MOS晶体管和电容器元件分别形成在第一元件区域和第二元件区域中。 在电压产生电路中，MOS晶体管的电流路径串联连接，并且电容器元件连接到MOS晶体管的源极或漏极。 接触插塞形成在源极或漏极上，以连接MOS晶体管或MOS晶体管之一以及电容器元件中的一个。 位于串联连接的最后级的MOS晶体管的栅极和接触插塞之间的距离大于串联连接中位于初始阶段的第二个MOS晶体管的距离。

公开(公告)号：US20110230041A1

公开(公告)日：2011-09-22

申请号：US13150768

申请日：2011-06-01

申请人： Hiraku CHAKIHARA ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku CHAKIHARA ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/283

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US08008703B2

公开(公告)日：2011-08-30

申请号：US12175201

申请日：2008-07-17

申请人： Mitsuhiro Noguchi ,  Minori Kajimoto

发明人： Mitsuhiro Noguchi ,  Minori Kajimoto

IPC分类号： H01L29/788

CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.

摘要翻译： 非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱 ，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离， 其形成在半导体衬底中。 第三井具有比第二井的第二部分更少的深度。

公开(公告)号：US07985678B2

公开(公告)日：2011-07-26

申请号：US12896933

申请日：2010-10-04

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/44

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US07915647B2

公开(公告)日：2011-03-29

申请号：US11858634

申请日：2007-09-20

申请人： Yoshiko Kato ,  Mitsuhiro Noguchi

发明人： Yoshiko Kato ,  Mitsuhiro Noguchi

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory concerning an example of the present invention comprises a cell array, a plurality of conducting wires extending from the cell array to a lead area, and a plurality of contact holes to arranged in the lead area so that a distance from the end of the cell array sequentially increases from one to the other of the plurality of conducting wires, each of the plurality of conducting wires having a first conducting wire portion having a first conducting wire width, a second conducting wire portion connected to the contact hole and having a second conducting wire width smaller than the first conducting wire width, and a third conducting wire portion electrically connecting the first conducting wire portion to the second conducting wire portion.

摘要翻译： 关于本发明的实例的非易失性半导体存储器包括单元阵列，从单元阵列延伸到引导区域的多个导线以及布置在引导区域中的多个接触孔，使得距离端部的距离 所述多个导线中的每个导线具有具有第一导线宽度的第一导线部分，连接到所述接触孔的第二导线部分，并且具有 第二导线宽度小于第一导线宽度;以及第三导线部分，其将第一导线部分电连接到第二导线部分。