公开(公告)号：US08922022B2

公开(公告)日：2014-12-30

申请号：US13356013

申请日：2012-01-23

申请人： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

发明人： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

摘要翻译： 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。

公开(公告)号：US08656325B2

公开(公告)日：2014-02-18

申请号：US13348850

申请日：2012-01-12

申请人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

发明人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/76 ,  G06F2217/78

摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

摘要翻译： 公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。 为了建立设计约束的目的，对短和长金属部件进行不同的处理。 对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者， 用作该短金属部件的设计约束。 对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。 本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。

公开(公告)号：US20120306048A1

公开(公告)日：2012-12-06

申请号：US13149108

申请日：2011-05-31

申请人： Baozhen Li ,  Chunyan E. Tian ,  Chih-Chao Yang

发明人： Baozhen Li ,  Chunyan E. Tian ,  Chih-Chao Yang

IPC分类号： H01L23/525 ,  H01L21/02

CPC分类号： H01L23/5256 ,  G11C17/16 ,  G11C29/785 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.

摘要翻译： 金属电可编程保险丝（eFuse）包括在金属条的两端处具有与宽金属线部分相邻的金属线的具有宽度大于金属带宽度的宽度的金属带。 条带宽度可以是光刻最小尺寸，并且金属条带的长度与条带宽度的比率大于5以在编程期间定位围绕金属条的中心的加热。 加热的本地化减少了用于编程金属eFuse所需的电力。 此外，在金属带的长于Blech长度的部分内的编程期间形成逐渐的温度梯度，使得金属的电迁移在金属带的中心部分逐渐发生。 金属线部分提供与金属eFuse相同的水平，以物理阻挡编程期间产生的碎屑。

公开(公告)号：US20120261793A1

公开(公告)日：2012-10-18

申请号：US13085568

申请日：2011-04-13

申请人： Chih-Chao Yang ,  Stephen M. Gates ,  Baozhen Li ,  Daniel C. Edelstein

发明人： Chih-Chao Yang ,  Stephen M. Gates ,  Baozhen Li ,  Daniel C. Edelstein

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.

摘要翻译： 一种改进的电熔丝（e-fuse）装置，包括具有第一顶表面的电介质层，嵌入介质层中的两个导电特征和熔丝元件。 每个导电特征具有第二顶表面和直接在第二顶表面上的金属帽。 每个金属盖具有在介电层的第一顶表面之上的第三顶表面。 熔丝元件位于每个金属盖的第三顶表面上，并位于介质层的第一顶表面上。 还提供了形成电熔丝装置的方法。

公开(公告)号：US20120080771A1

公开(公告)日：2012-04-05

申请号：US12898340

申请日：2010-10-05

申请人： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

发明人： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

IPC分类号： H01L27/08 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L21/76805 ,  H01L25/0657 ,  H01L28/91 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

摘要翻译： 本发明提供一种3D通孔电容器及其形成方法。 电容器包括在基板上的绝缘层。 绝缘层具有通孔，其具有侧壁和底部。 第一电极覆盖通孔的侧壁和底部的至少一部分。 第一高k电介质材料层覆盖在第一电极上。 第一导电板在第一高k电介质材料层之上。 第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。 在通孔的剩余部分中形成第二电极。 第一导电板基本上平行于第一电极并且不与第一和第二电极接触。 还提供了这种3D通孔电容器的阵列。

公开(公告)号：US07981771B2

公开(公告)日：2011-07-19

申请号：US12132806

申请日：2008-06-04

申请人： Baozhen Li

发明人： Baozhen Li

IPC分类号： H01L21/326

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L21/76849 ,  Y10S438/927

摘要： The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect.

摘要翻译： 本发明一般涉及半导体器件，更具体地涉及用于增强互连中的电迁移（EM）性能的结构和方法。 一种方法包括形成互连，在互连上形成帽，并且在帽中形成多个孔以改善互连的电迁移性能。

公开(公告)号：US07955971B2

公开(公告)日：2011-06-07

申请号：US12482777

申请日：2009-06-11

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel Edelstein ,  Baozhen Li

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel Edelstein ,  Baozhen Li

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.

摘要翻译： 一种制造结构的结构和方法。 该结构包括：介电层中的沟槽; 导电衬垫，导电芯导体和填充所述衬套和所述芯导体之间的空隙的导电填充材料。

公开(公告)号：US07830019B2

公开(公告)日：2010-11-09

申请号：US12431289

申请日：2009-04-28

申请人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

IPC分类号： H01L23/04

CPC分类号： H01L21/76865 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76886

摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。

公开(公告)号：US20100176514A1

公开(公告)日：2010-07-15

申请号：US12351367

申请日：2009-01-09

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Baozhen Li

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Baozhen Li

IPC分类号： H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/02068 ,  H01L21/311 ,  H01L21/32136 ,  H01L21/76885 ,  H01L21/76886

摘要： The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap.

摘要翻译： 本发明包括铜互连结构，其包括具有电介质的贵金属盖，所述绝缘体紧邻于从贵金属帽凹入的铜/贵金属帽接口。

公开(公告)号：US07649262B2

公开(公告)日：2010-01-19

申请号：US12537328

申请日：2009-08-07

申请人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

发明人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC分类号： H01L23/48

CPC分类号： H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

摘要翻译： 用于抑制半导体处理中的局部金属沉淀形成（LMPF）的结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。