公开(公告)号：US20250157936A1

公开(公告)日：2025-05-15

申请号：US19020976

申请日：2025-01-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Ravindranath T. Kollipara

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.

公开(公告)号：US20250046715A1

公开(公告)日：2025-02-06

申请号：US18923503

申请日：2024-10-22

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US12176803B2

公开(公告)日：2024-12-24

申请号：US18471868

申请日：2023-09-21

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Sanjay Dabral

IPC: H02M1/15 ,  G06F1/3206 ,  H02M3/158

Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

公开(公告)号：US20240103238A1

公开(公告)日：2024-03-28

申请号：US18458892

申请日：2023-08-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  SivaChandra Jangam

IPC: G02B6/42

CPC classification number: G02B6/428 ,  G02B6/4279 ,  G02B6/4283 ,  G02B6/4293

Abstract: A system in package structure and method of fabrication using wafer reconstitution are described. In an embodiment a 3D system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. Second package level components can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while the first package level components can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds. Dies within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

公开(公告)号：US20240047353A1

公开(公告)日：2024-02-08

申请号：US18488561

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/58

CPC classification number: H01L23/528 ,  H01L23/5386 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0652 ,  H01L23/585 ,  H01L22/20

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US11735526B2

公开(公告)日：2023-08-22

申请号：US17699563

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/49816 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H05K1/111 ,  H05K1/181 ,  H01L24/16 ,  H01L2224/16225 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20230052432A1

公开(公告)日：2023-02-16

申请号：US17931343

申请日：2022-09-12

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/498

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US20230040308A1

公开(公告)日：2023-02-09

申请号：US17397834

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US20220102280A1

公开(公告)日：2022-03-31

申请号：US17321080

申请日：2021-05-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/66

Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

公开(公告)号：US11158607B2

公开(公告)日：2021-10-26

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.