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51.发明授权
公开(公告)号：US6150969A
公开(公告)日：2000-11-21
申请号：US163235
申请日：1998-09-29
CPC分类号： G06F1/025 , H03M3/388 , H03M7/304 , H03M3/506 , H03M7/3026
摘要： A delta sigma modulator of at least second order includes correction means applied to each feedback loop in the modulator, to account for systemic nonlinear output distortions. Since the output distortion is nonlinear, the correction applied to each feedback loop is nontrivially different. Such a corrected delta sigma modulator may be used in a demodulator including an output digital to analog converter (DAC) to account for systemic imperfections in the pulses formed by the DAC. The corrected delta sigma modulator is also useful in correcting output errors associated with high quality multilevel demodulators and class D power amplifiers. The corrected delta sigma modulator may be one bit or multilevel.
摘要翻译： 至少二阶的ΔΣ调制器包括施加到调制器中的每个反馈回路的校正装置，以解决系统非线性输出失真。 由于输出失真是非线性的，所以施加到每个反馈回路的校正是非常不同的。 这种校正的Δ-Σ调制器可以用在包括输出数模转换器（DAC）的解调器中，以解决由DAC形成的脉冲中的系统缺陷。 校正的Δ-Σ调制器也可用于校正与高质量多电平解调器和D类功率放大器相关联的输出误差。 校正的Δ-Σ调制器可以是一位或多级。
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公开(公告)号：US5815102A
公开(公告)日：1998-09-29
申请号：US662873
申请日：1996-06-12
CPC分类号： H03M7/304 , G06F1/025 , H03M3/388 , H03M3/506 , H03M7/3026
摘要： A digital to analog (D/A) converter for hearing aids and the like includes a delta sigma modulator and a duty cycle demodulator. The delta sigma modulator converts medium rate, high resolution data into medium rate, medium resolution data, and the duty cycle demodulator converts the medium rate, medium resolution data into low resolution, high rate data. The duty cycle demodulator utilizes a lookup function to format the output data in a format having lowered transition rates, resulting in lower power use. The delta sigma converter may include a correction factor in at least one of its feedback loops to compensate for the characteristics of the output data from the duty cycle demodulator.
摘要翻译： 用于助听器的数模（D / A）转换器等包括ΔΣ调制器和占空比解调器。 ΔΣ调制器将中等速率，高分辨率数据转换为中等速率，中等分辨率数据，占空比解调器将中等速率，中等分辨率数据转换为低分辨率，高速率数据。 占空比解调器利用查找功能将输出数据格式化为具有降低的转换速率的格式，导致较低的功率使用。 ΔΣ转换器可以在其反馈回路中的至少一个中包括校正因子，以补偿来自占空比解调器的输出数据的特性。
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公开(公告)号：US4106011A
公开(公告)日：1978-08-08
申请号：US625611
申请日：1975-10-24
CPC分类号： H03M11/003
摘要： A simplified keyboard for a terminal device, calculator, or the like, in which each key is sequentially scanned and parallel key code data is sent to an entry register. A pair of flip-flops in combination with firmware ascertain that only valid key code data is sent to the entry register for utilization by the system, providing double entry and key bounce protection. The firmware further provides N-key rollover and auto repeat with a variable repeat rate, and expands the keyboard from a single-mode to an eight-mode capability.
摘要翻译： 用于终端设备，计算器等的简化键盘，其中每个键被顺序扫描，并且并行键码数据被发送到入口寄存器。 与固件组合的一对触发器确定只有有效的密钥代码数据被发送到入口寄存器以供系统利用，提供双重输入和关键跳跃保护。 该固件进一步提供N键翻转和自动重复的可重复速率，并将键盘从单模式扩展到八模式功能。
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54.发明授权Adjustable constant current source with continuous conduction mode (“CCM”) and discontinuous conduction mode (“DCM”) operation 有权具有连续导通模式（“CCM”）和不连续导通模式（“DCM”）操作的可调节恒流源公开(公告)号：US08179110B2
公开(公告)日：2012-05-15
申请号：US12242009
申请日：2008-09-30
IPC分类号： G05F1/40
CPC分类号： H02M3/156 , H02M3/158 , H05B33/0815 , Y02B20/347
摘要： A converter system and method of operating a converter system are disclosed. The converter system comprises a converter power stage that can operate in a Discontinuous Conduction Mode (DCM) in a range of output currents and a Continuous Conduction Mode (CCM) in another range of output currents. The converter power stage includes at least an inductor with an inductor value and a control switch. The converter power stage provides an average current. A current controller is coupled to the converter power stage. When the converter power stage operates in DCM, the converter power stage provides the average current and the current controller is configured to measure the inductor value of the inductor. Furthermore, the current controller can also be configured to measure an input-to-output conversion ratio from the converter power stage.
摘要翻译： 公开了一种转换器系统和操作转换器系统的方法。 转换器系统包括转换器功率级，其可以在输出电流范围内的连续导通模式（DCM）中工作，并且在另一范围的输出电流中可操作连续导通模式（CCM）。 转换器功率级至少包括具有电感值的电感器和控制开关。 转换器功率级提供平均电流。 电流控制器耦合到转换器功率级。 当转换器功率级在DCM中工作时，转换器功率级提供平均电流，并且电流控制器被配置为测量电感器的电感值。 此外，电流控制器还可以被配置为从转换器功率级测量输入到输出转换比。
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55.发明授权Systems and methods for clock mode determination utilizing master clock frequency measurements 有权使用主时钟频率测量的时钟模式确定的系统和方法公开(公告)号：US07456765B1
公开(公告)日：2008-11-25
申请号：US11136030
申请日：2005-05-24
IPC分类号： H03M1/00
CPC分类号： H03M1/1265 , H04J3/0685
摘要： A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and a characteristic of an additional data clock signal to an operating mode of the data converter. In another embodiment, the mapping system maps measurements of the master clock frequency alone to a data converter operating mode. In a further embodiment, the measurement circuitry measures the master clock frequency of a master clock signal, which is received directly from a master clock signal source without a modification in the master clock frequency.
摘要翻译： 用于确定数据转换器时钟操作模式的系统包括测量主时钟信号的主时钟频率和数据时钟信号的频率与主时钟频率之间的频率比的测量电路。 映射系统将主时钟频率，频率比和附加数据时钟信号的特性的测量结果映射到数据转换器的操作模式。 在另一个实施例中，映射系统将主时钟频率的测量单独地映射到数据转换器操作模式。 在另一个实施例中，测量电路测量主时钟信号的主时钟频率，主时钟信号直接从主时钟信号源接收而不改变主时钟频率。
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56.发明申请Power Factor Correction (PFC) Controller and Method Using a Finite State Machine to Adjust the Duty Cycle of a PWM Control Signal 有权功率因数校正（PFC）控制器和使用有限状态机调节PWM控制信号的占空比的方法公开(公告)号：US20080272748A1
公开(公告)日：2008-11-06
申请号：US12107613
申请日：2008-04-22
IPC分类号： G05F1/70
CPC分类号： H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
摘要： A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
摘要翻译： 功率因数校正（PFC）控制器和方法使用有限状态机调节脉宽调制（PWM）切换控制信号的占空比。 PFC控制器具有目标电流发生器，其接收链路输出电压并产生与整流线路输入电压成比例的目标电流。 PFC控制器还包括输出双电平电流比较结果信号的比较器。 响应于两电平电流比较结果信号的有限状态机产生开关控制信号，该开关控制信号具有调节用于控制开关的占空比，使得感测到的电流与整流线路输入电压近似成比例，使得功率 进行因子校正。
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57.发明授权Systems and methods for clock mode determination utilizing prioritization criteria 有权使用优先级标准的时钟模式确定的系统和方法公开(公告)号：US07352303B1
公开(公告)日：2008-04-01
申请号：US11135995
申请日：2005-05-24
IPC分类号： H03M7/00
CPC分类号： H03M1/1255 , G11B20/14
摘要： A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.
摘要翻译： 一种用于确定数据转换器操作模式的系统包括测量电路，其测量主时钟信号的主时钟频率，而无需主时钟信号源的频率修改，并且测量数据时钟信号的频率与数据时钟信号的频率之间的频率比 主时钟频率。 映射系统将主时钟频率和频率比的测量结果映射到数据转换器的操作模式。 在其他实施例中，映射系统基于模式优先级约束将主时钟频率和频率比的测量映射到数据转换器的操作模式。 在另外的实施例中，映射系统通过缩小主时钟分频比的选择并随后从频率比确定操作模式，将主时钟频率和频率比的测量值映射到数据转换器的工作模式。
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公开(公告)号：US07350001B1
公开(公告)日：2008-03-25
申请号：US10346532
申请日：2003-01-17
CPC分类号： H03M7/14
摘要： Methods and Apparatuses are provided for automatically converting a word length of sample data being transmitted over a serial link. A serial interface transmits and/or receives one or more data words comprising digital signals, a bit clock synchronizes transmission of individual bits, and a word clock is used to group the bits into sample words. A desired word length is determined based on the relationship between the bit clock and the word clock during the transmission or reception of a data word. Based on the desired word length, the sample data is either truncated or padded, and an appropriate amount of dither is added to the sample words to reduce the distortion and quantization artifacts introduced by the word length conversion.
摘要翻译： 提供了用于自动转换通过串行链路发送的样本数据的字长的方法和装置。 串行接口发送和/或接收包括数字信号的一个或多个数据字，位时钟同步各个位的传输，并且字时钟用于将位分组成采样字。 在数据字的发送或接收期间，基于位时钟和字时钟之间的关系来确定期望的字长。 基于期望的字长度，采样数据被截断或填充，并且适当量的抖动被添加到采样字以减少由字长转换引入的失真和量化伪像。
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59.发明授权Systems and methods for clock mode determination utilizing operating conditions measurement 有权使用操作条件测量的时钟模式确定的系统和方法公开(公告)号：US07236109B1
公开(公告)日：2007-06-26
申请号：US11135866
申请日：2005-05-24
IPC分类号： H03M7/00
CPC分类号： G11B20/10009 , G11B20/10222
摘要： A system for determining a data converter operating mode includes measurement circuitry which measures a master clock frequency, measures a frequency ratio between a frequency of a data clock signal and the master clock frequency, and measures a selected operating condition of the data converter. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and the selected operating condition, to an operating mode of the data converter. In another embodiment, the measurement circuitry adjusts the measurement of the master clock frequency in response to a measurement of the operating conditions of the data converter. In a further embodiment, user input information varies the measurement of the master clock frequency.
摘要翻译： 用于确定数据转换器操作模式的系统包括测量主时钟频率的测量电路，测量数据时钟信号的频率与主时钟频率之间的频率比，并且测量数据转换器的所选择的操作条件。 映射系统将主时钟频率，频率比和所选择的操作条件的测量值映射到数据转换器的操作模式。 在另一个实施例中，测量电路响应于数据转换器的操作条件的测量来调整主时钟频率的测量。 在另一实施例中，用户输入信息改变主时钟频率的测量。
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60.发明授权Noise-shapers and filters with noise shaping quantizers and systems and methods using the same 有权具有噪声整形量化器的噪声整形器和滤波器以及使用其的系统和方法公开(公告)号：US07212874B2
公开(公告)日：2007-05-01
申请号：US10397556
申请日：2003-03-26
CPC分类号： H03H17/04 , H03B29/00 , H03M7/3028 , H03M7/304
摘要： A noise shaping system including an inner loop and outer noise shaping loops. The inner noise shaping loop includes an inner loop filter and a quantizer for quantizing an output of the inner loop filter. The outer noise shaping loop includes an outer loop filter having an input receiving feedback from the quantizer of the inner noise shaping loop and an output driving an input of the inner loop filter of the inner noise shaping loop.
摘要翻译： 一种噪声整形系统，包括内环和外噪声整形环。 内部噪声整形环路包括用于量化内部环路滤波器的输出的内部环路滤波器和量化器。 外部噪声整形回路包括外部环路滤波器，其具有接收来自内部噪声整形环路的量化器的反馈的输入和驱动内部噪声整形环路的内部环路滤波器的输入的输出。
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