Screening Method And Apparatus For Use In Intaglio Printing
    51.
    发明申请
    Screening Method And Apparatus For Use In Intaglio Printing 有权
    用于凹版印刷的筛选方法和装置

    公开(公告)号:US20140033937A1

    公开(公告)日:2014-02-06

    申请号:US13996967

    申请日:2011-12-24

    申请人: Haifeng Li Bin Yang

    发明人: Haifeng Li Bin Yang

    IPC分类号: G03F5/20

    CPC分类号: G03F5/20 H04N1/4055

    摘要: The present application provides a screen method for intaglio printing, comprising: dividing multiple classes of regions according to a brightness range; and generating screen dots with various screen patterns for the grouped classes of regions. The present application also provides a screen device for intaglio printing, comprising: a dividing module configured to group multiple classes of regions according to the brightness range; and a generating module configured to generate screen dots with various screen patterns for the grouped classes of regions. Since multiple kinds of screen patterns are applied in the technical solutions in present application, the problem, i.e., water ripple will occur in the prior art, may be addressed, so as to improve the quality of printing.

    摘要翻译: 本申请提供了一种用于凹版印刷的屏幕方法,包括:根据亮度范围划分多个类别的区域; 并且为分组的区域类别生成具有各种屏幕图案的屏幕点。 本申请还提供了一种用于凹版印刷的屏幕装置,包括:分割模块,被配置为根据亮度范围对多个类别的区域进行分组; 以及生成模块,被配置为生成用于所述分组的区域类别的各种屏幕图案的屏幕点。 由于在本申请中的技术方案中应用了多种屏幕图案,所以可以解决现有技术中出现的水波纹问题,以提高打印质量。

    Integrated microchannel synthesis and separation
    52.
    发明授权
    Integrated microchannel synthesis and separation 有权
    集成微通道的合成和分离

    公开(公告)号:US08497308B2

    公开(公告)日:2013-07-30

    申请号:US12439872

    申请日:2007-09-05

    IPC分类号: C07C27/00

    摘要: A process for carrying out at least two unit operations in series, the process comprising the step of: (a) directing a feed stream into an integrated assembly which comprises a first microchannel unit operation upon at least one chemical of the feed stream to generate a distributed output stream that exits the first microchannel unit operation in a first set of discrete microchannels isolating flow through the discrete microchannels; and (b) directing the distributed output stream of the first microchannel unit operation into a second microchannel unit operation as a distributed input stream, to continue isolating flow between the first set of discrete microchannels, and conducting at least one operation upon at least one chemical of the input stream to generate a product stream that exits the second microchannel unit operation, where the first microchannel unit operation and the second unit operation share a housing.

    摘要翻译: 一种用于串联进行至少两个单元操作的方法,该方法包括以下步骤:(a)将进料流引导到集成组件中,其包括在进料流的至少一种化学品上的第一微通道单元操作以产生 在第一组离散微通道中离开第一微通道单元操作的分布式输出流,其隔离通过离散微通道的流动; 和(b)将第一微通道单元操作的分布式输出流引导到作为分布式输入流的第二微通道单元操作中,以继续隔离第一组离散微通道之间的流动,并且至少一种化学物质进行至少一种操作 以产生离开第二微通道单元操作的产品流,其中第一微通道单元操作和第二单元操作共享外壳。

    Method to form uniform silicide by selective implantation
    53.
    发明授权
    Method to form uniform silicide by selective implantation 有权
    通过选择性植入形成均匀硅化物的方法

    公开(公告)号:US08492275B2

    公开(公告)日:2013-07-23

    申请号:US13186519

    申请日:2011-07-20

    IPC分类号: H01L21/44

    摘要: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

    摘要翻译: 方法通过在衬底内和/或衬底上形成多个器件的至少一部分形成集成电路结构,并且在邻近器件的衬底上的层间电介质层中图案化沟槽。 图案形成相对较窄的沟槽和较宽的沟槽。 然后,所述方法对沟槽进行补偿材料的成角度注入。 成角度的植入物的角度相对于在较窄沟槽的底部注入衬底的区域中的补偿材料的量,在较宽沟槽底部的衬底区域中植入更大浓度的补偿材料。 然后,该方法将金属材料沉积在沟槽内,并加热金属材料以从金属材料形成硅化物。

    Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device
    56.
    发明授权
    Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device 失效
    具有减小的结漏电的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号:US08349716B2

    公开(公告)日:2013-01-08

    申请号:US12911186

    申请日:2010-10-25

    IPC分类号: H01L21/336 H01L21/04

    摘要: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

    摘要翻译: 公开了一种具有p-n结的半导体器件,其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说,形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层,并且将掺杂剂注入到金属硅化物层中。 执行退火处理,使掺杂剂朝向金属硅化物半导体层界面迁移,使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果,硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度,这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

    Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor material
    58.
    发明授权
    Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor material 有权
    用于改进隔离区域和无缺陷活性半导体材料的半导体器件制造方法

    公开(公告)号:US08198170B2

    公开(公告)日:2012-06-12

    申请号:US12905805

    申请日:2010-10-15

    申请人: Man Fai Ng Bin Yang

    发明人: Man Fai Ng Bin Yang

    IPC分类号: H01L21/762

    摘要: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.

    摘要翻译: 提供了半导体器件结构的制造方法。 该器件结构具有一层硅层和一层覆盖硅层的二氧化硅层,该方法开始于通过去除一部分二氧化硅和一部分硅来形成隔离凹槽。 隔离凹部填充有应力诱导性氮化硅,然后去除二氧化硅,使得应力诱导性氮化硅突出于硅上方。 接下来,暴露的硅被热氧化以形成覆盖在硅上的二氧化硅硬掩模材料。 此后,去除二氧化硅硬掩模材料的第一部分以露出硅的可接近表面,同时留下二氧化硅硬掩模材料的第二部分完好无损。 接下来,从硅的可接近表面外延生长硅锗。