公开(公告)号：US20120286361A1

公开(公告)日：2012-11-15

申请号：US13107191

申请日：2011-05-13

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42368 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66659 ,  H01L29/7835

摘要： The present invention discloses a high voltage device which includes: a substrate having a first isolation structure to define a device region; a source and a drain in the device region; a gate on the substrate and between the source and the drain; and a second isolation structure including: a first isolation region on the substrate and between the source and the drain, wherein from top view, the first isolation region is partially or totally covered by the gate; and a second isolation region in the substrate and below the gate, wherein the second isolation region has a depth in the substrate which is deeper than the depth of the first isolation region in the substrate, and the length of the second isolation region in a direction along an imaginary line connecting the source and the drain does not exceed one-third length of the first isolation region.

摘要翻译： 本发明公开了一种高电压装置，其包括：具有第一隔离结构以限定器件区域的衬底; 设备区域中的源极和漏极; 基板上的栅极和源极与漏极之间的栅极; 以及第二隔离结构，包括：在所述衬底上以及所述源极和漏极之间的第一隔离区域，其中从顶视图看，所述第一隔离区域被所述栅极部分或全部覆盖; 以及在所述衬底中并在所述栅极下方的第二隔离区域，其中所述第二隔离区域在所述衬底中具有比所述衬底中的所述第一隔离区域的深度更深的深度，以及所述第二隔离区域在所述衬底中的方向上的长度 沿着连接源极和漏极的假想线不超过第一隔离区域的三分之一长度。

公开(公告)号：US20120193707A1

公开(公告)日：2012-08-02

申请号：US13065569

申请日：2011-03-24

申请人： Tsung-Yi Huang ,  Chien-Wei Chiu

发明人： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66704 ,  H01L29/7824 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78696

摘要： The present invention discloses a high voltage multigate device and a manufacturing method thereof. The high voltage multigate device includes: a semiconductor fin doped with first conductive type impurities; a dielectric layer, which overlays a portion of the semiconductor fin; a gate which overlays the dielectric layer; a drain doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a drift region or a well doped with second conductive type impurities, which is formed in the semiconductor fin at least between the drain and the gate.

摘要翻译： 本发明公开了一种高压多电位装置及其制造方法。 高电压多器件包括：掺杂有第一导电类型杂质的半导体鳍片; 介电层，覆盖半导体鳍片的一部分; 覆盖介电层的栅极; 掺杂有第二导电类型杂质的漏极，其形成在半导体鳍片中或耦合到半导体鳍片; 掺杂有第二导电类型杂质的源，其形成在半导体鳍片中或耦合到半导体鳍片，其中漏极和源极位于栅极的不同侧; 以及漂移区或掺杂有第二导电类型杂质的阱，其至少在漏极和栅极之间形成在半导体鳍片中。

公开(公告)号：US20120161236A1

公开(公告)日：2012-06-28

申请号：US13373766

申请日：2011-11-29

申请人： Tsung-Yi Huang ,  Jin-Lian Su

发明人： Tsung-Yi Huang ,  Jin-Lian Su

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41758 ,  H01L27/0277 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7835

摘要： The present invention discloses an electrostatic discharge protection device and a manufacturing method thereof. The electrostatic discharge protection device includes: a substrate, a gate, two N type lightly doped drains, an N type source, an N type drain, and two N type doped regions extending downward beneath and in contact with the source and drain respectively, such that when the source and drain are conducted with each other, at least part of the current flows through the two downwardly extending doped regions to increase the electrostatic discharge protection voltage of the electrostatic discharge protection device.

公开(公告)号：US08114725B1

公开(公告)日：2012-02-14

申请号：US12914291

申请日：2010-10-28

申请人： Tsung-Yi Huang ,  Ching-Yao Yang

发明人： Tsung-Yi Huang ,  Ching-Yao Yang

IPC分类号： H01L21/338 ,  H01L21/336

CPC分类号： H01L29/66598 ,  H01L21/26586

摘要： The present invention discloses a method of manufacturing MOS device having a lightly doped drain (LDD) structure. The method includes: providing a first conductive type substrate; forming an isolation region in the substrate to define a device area; forming a gate structure in the device area, the gate structure having a dielectric layer, a stack layer, and a spacer layer on the sidewalls of the stack layer; implanting second conductive type impurities into the substrate with a tilt angle to form an LDD structure, wherein at least some of the impurities are implanted into the substrate through the spacer to form part of the LDD structure below the spacer layer; and implanting second conductive type impurities into the substrate to form source and drain.

摘要翻译： 本发明公开了一种制造具有轻掺杂漏极（LDD）结构的MOS器件的方法。 该方法包括：提供第一导电型衬底; 在所述衬底中形成隔离区以限定器件区域; 在所述器件区域中形成栅极结构，所述栅极结构在所述堆叠层的侧壁上具有介电层，堆叠层和间隔层; 以倾斜角度将第二导电类型的杂质注入到衬底中以形成LDD结构，其中至少一些杂质通过间隔物注入到衬底中以形成在间隔层下方的LDD结构的一部分; 以及将第二导电类型杂质注入到所述衬底中以形成源极和漏极。

公开(公告)号：US07915677B2

公开(公告)日：2011-03-29

申请号：US12329285

申请日：2008-12-05

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/78

摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

公开(公告)号：US07888216B2

公开(公告)日：2011-02-15

申请号：US12757242

申请日：2010-04-09

申请人： Yu Wen Chen ,  Fu-Hsin Chen ,  Tsung-Yi Huang ,  Yt Tsai

发明人： Yu Wen Chen ,  Fu-Hsin Chen ,  Tsung-Yi Huang ,  Yt Tsai

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/66689 ,  H01L29/7817

摘要： A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.

摘要翻译： 制造半导体器件的方法包括在衬底中形成包括第一类掺杂剂的阱区; 在所述阱区中形成包含不同于所述第一类型掺杂剂的第二类型掺杂剂的基极区; 以及在包括第一类型掺杂剂的衬底源极和漏极区域中形成。 该方法还包括在衬底上形成横向插入在源区和漏区之间的栅电极; 以及在所述衬底上形成栅极间隔件，所述栅极间隔件横向设置在所述源区域和所述栅电极之间，邻近所述栅电极的一侧并且具有嵌入其中的导电特征。 阱区域围绕漏极区域和基极区域，并且基极区域部分地设置在围绕源极区域的栅极电极周围，该源极区域限定栅极电极下方的沟道，其长度基本上小于栅电极的长度的一半。

公开(公告)号：US20100006935A1

公开(公告)日：2010-01-14

申请号：US12170246

申请日：2008-07-09

申请人： Eric Huang ,  Tsung-Yi Huang ,  Fu-Hsin Chen ,  Chyi-Chyuan Huang ,  Chung-Yeh Wu

发明人： Eric Huang ,  Tsung-Yi Huang ,  Fu-Hsin Chen ,  Chyi-Chyuan Huang ,  Chung-Yeh Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.

摘要翻译： 半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所​​述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 所述第一导电类型的场环占据所述HVW的顶部部分，其中所述预HVW，所述HVW和所述场环中的至少一个包括至少两个隧道; 在场环上的绝缘区域和HVW的一部分; 在HVW中的漏极区域并且邻近绝缘区域; 绝缘区域的一部分上的栅电极; 以及栅极电极的与漏极区域相反的一侧的源极区域。

公开(公告)号：US20090085101A1

公开(公告)日：2009-04-02

申请号：US12329285

申请日：2008-12-05

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

摘要翻译： 提供具有高击穿电压和低导通电阻的半导体器件。 一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。 在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。 场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。 晶体管的源极和漏极区位于高压P阱和高压N阱中。 可选地，在场电介质下的N阱区域中形成P场环。 在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。

公开(公告)号：US07476591B2

公开(公告)日：2009-01-13

申请号：US11581178

申请日：2006-10-13

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

摘要翻译： 提供具有高击穿电压和低导通电阻的半导体器件。 一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。 在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。 场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。 晶体管的源极和漏极区位于高压P阱和高压N阱中。 可选地，在场电介质下的N阱区域中形成P场环。 在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。

公开(公告)号：US20090001462A1

公开(公告)日：2009-01-01

申请号：US12205961

申请日：2008-09-08

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

摘要翻译： 半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所​​述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。