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    Semiconductor composite film with heterojunction and manufacturing method thereof
    1.
    发明授权
    Semiconductor composite film with heterojunction and manufacturing method thereof 有权
    具有异质结的半导体复合膜及其制造方法

    公开(公告)号：US09245746B2

    公开(公告)日：2016-01-26

    申请号：US14048971

    申请日：2013-10-08

    申请人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

    发明人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

    IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/12

    CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30612 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/7845 ,  H01L29/7849

    摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

    摘要翻译： 本发明公开了一种具有异质结的半导体复合膜及其制造方法。 半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步 包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。 该凹槽用于减轻半导体复合膜中的应变。

    High voltage device and manufacturing method thereof
    6.
    发明授权
    High voltage device and manufacturing method thereof 有权
    高压器件及其制造方法

    公开(公告)号：US08859373B2

    公开(公告)日：2014-10-14

    申请号：US14056613

    申请日：2013-10-17

    申请人： Tsung-Yi Huang ,  Chien-Wei Chiu

    发明人： Tsung-Yi Huang ,  Chien-Wei Chiu

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

    CPC分类号： H01L29/66681 ,  H01L29/0623 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7813 ,  H01L29/7835

    摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.

    摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件形成在衬底中。 高电压装置包括：栅极，源极和漏极，漂移区和缓解区。 栅极形成在衬底的上表面上。 源极和漏极分别位于栅极下方的两侧，源极和漏极由栅极分开。 漂移区域至少位于栅极和漏极之间。 缓冲区形成在漂移区下方，漂移区具有靠近源的边。 漂移区域的这个边缘与缓解区域之间的垂直距离小于或等于漂移区域的深度的五倍。

    High Electron Mobility Transistor and Manufacturing Method Thereof
    8.
    发明申请
    High Electron Mobility Transistor and Manufacturing Method Thereof 审中-公开
    高电子迁移率晶体管及其制造方法

    公开(公告)号：US20140061658A1

    公开(公告)日：2014-03-06

    申请号：US13603392

    申请日：2012-09-04

    申请人： Chien-Wei Chiu ,  Tsung-Yi Huang

    发明人： Chien-Wei Chiu ,  Tsung-Yi Huang

    IPC分类号： H01L29/778 ,  H01L21/338

    CPC分类号： H01L29/1033 ,  H01L21/76224 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7787

    摘要： The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate.

    摘要翻译： 本发明公开了一种增强型高电子迁移率晶体管（HEMT），其包括：P型氮化镓（GaN）层; 阻挡层，其形成在GaN层上并连接到GaN层; 形成在GaN层上并连接到GaN层的电介质层，其中阻挡层不与电介质层的至少一部分重叠; 栅极，其形成在用于接收栅极电压的电介质层上; 以及源极和漏极，其分别形成在GaN层上的栅极的两侧; 其中在GaN层和阻挡层的结合处形成二维电子气（2DEG），其不包括在栅极下方的结的一部分，并且当存在时，2DEG不将源电连接到漏极 没有电压施加到门。

    Double diffused metal oxide semiconductor device
    9.
    发明授权
    Double diffused metal oxide semiconductor device 有权
    双扩散金属氧化物半导体器件

    公开(公告)号：US08575693B1

    公开(公告)日：2013-11-05

    申请号：US13480360

    申请日：2012-05-24

    申请人： Tsung-Yi Huang ,  Chien-Wei Chiu ,  Chien-Hao Huang

    发明人： Tsung-Yi Huang ,  Chien-Wei Chiu ,  Chien-Hao Huang

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681

    摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed.

    摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）装置。 DMOS器件形成在衬底中，并且包括高电压阱，第一场氧化物区域，第一栅极，第一源极，漏极，体区域，体电极，第二场氧化物区域，第二栅极 ，和第二个来源。 第二场氧化物区域和第一场氧化物区域被高电压井和身体区域分开。 第二栅极的一部分在第二场氧化物区域上，第二栅极的另一部分位于主体区域上。 第二栅极电连接到第一栅极，并且第二源极电连接到第一源极，使得当DMOS器件导通时，形成表面沟道和埋入沟道。

    HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    高压器件及其制造方法

    公开(公告)号：US20130270634A1

    公开(公告)日：2013-10-17

    申请号：US13445151

    申请日：2012-04-12

    申请人： Tsung-Yi Huang ,  Chien-Wei Chiu

    发明人： Tsung-Yi Huang ,  Chien-Wei Chiu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate. A low voltage device is also formed in the substrate. The high voltage device includes a drift region, a gate, a source, a drain, and a mitigation region. The mitigation region has a second conductive type, and is formed in the drift region between the gate and drain. The mitigation region is formed by a process step which also forms a lightly doped drain (LDD) region in the low voltage device.

    摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件形成在第一导电型衬底中。 在基板中也形成低压器件。 高电压装置包括漂移区域，栅极，源极，漏极和缓解区域。 缓解区域具有第二导电类型，并且形成在栅极和漏极之间的漂移区域中。 缓解区域由在低电压装置中也形成轻掺杂漏极（LDD）区的工艺步骤形成。