公开(公告)号：US20110121426A1

公开(公告)日：2011-05-26

申请号：US12626078

申请日：2009-11-25

申请人： Ming-Sheng Yang ,  Cheng-Feng Peng ,  Jia-Fu Jhang

发明人： Ming-Sheng Yang ,  Cheng-Feng Peng ,  Jia-Fu Jhang

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： According to an embodiment of the invention, an electronic device with a fuse structure is provided. The electronic device includes a substrate, at least a conducting layer formed in or on the substrate and having a fuse area, and at least a lens disposed overlying the fuse area of the conducting layer, wherein the lens is substantially aligned with the fuse area and there is no optical device disposed between the lens and the fuse area.

摘要翻译： 根据本发明的实施例，提供了一种具有熔丝结构的电子设备。 电子器件包括衬底，至少形成在衬底中或衬底上并具有熔丝区域的导电层，以及至少设置在导电层的熔丝区域上方的透镜，其中透镜基本上与保险丝区域对准， 在透镜和保险丝区域之间没有设置光学装置。

公开(公告)号：US20060199381A1

公开(公告)日：2006-09-07

申请号：US11306193

申请日：2005-12-19

申请人： Hsueh-Chung Chen ,  Teng-Chun Tsai ,  Ming-Sheng Yang

发明人： Hsueh-Chung Chen ,  Teng-Chun Tsai ,  Ming-Sheng Yang

IPC分类号： H01L21/4763

CPC分类号： C25D21/10 ,  C25D5/04 ,  C25D17/001 ,  H01L21/2885

摘要： An improved electro-chemical deposition copper (ECD-Cu) apparatus and a method of preventing cavities in an ECD-Cu thin film are provided. The electro-chemical deposition apparatus has a bath tank, an anode positioned in the bath tank, and a spin plate for positioning a semiconductor wafer that is used as a cathode. The method, by alternating a spin direction of the spin plate between a clockwise direction and a counterclockwise direction, every 1 to 10 seconds, prevents an electrolyte solution of the bath tank from forming a stable vortex, and suppresses a phenomenon of forming cavities in the ECD-Cu thin film when bubbles of the vortex adhere to the wafer surface.

摘要翻译： 提供改进的电化学沉积铜（ECD-Cu）装置和防止ECD-Cu薄膜中的空穴的方法。 电化学沉积装置具有浴缸，位于浴槽中的阳极和用作定位用作阴极的半导体晶片的旋转板。 该方法通过使旋转板的旋转方向在顺时针方向和逆时针方向之间每1〜10秒交替，防止浴槽的电解液形成稳定的涡流，并且抑制在该槽中形成空腔的现象 ECD-Cu薄膜当漩涡气泡粘附到晶片表面时。

公开(公告)号：US06917109B2

公开(公告)日：2005-07-12

申请号：US10295062

申请日：2002-11-15

申请人： Water Lur ,  David Lee ,  Kuang-Chih Wang ,  Ming-Sheng Yang

发明人： Water Lur ,  David Lee ,  Kuang-Chih Wang ,  Ming-Sheng Yang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/48

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

摘要翻译： 公开了一种气隙结构和形成方法，用于显着减少集成电路器件中的相邻互连，金属线或其他特征之间的不需要的电容。 空气间隙在期望被隔离的互连之上延伸并且还可以另外延伸，从而最小化线之间的边缘场。 集成气隙结构和形成方法可以与镶嵌或常规集成电路金属化方案结合使用。 此外，可以制造多个级别的集成气隙结构以适应多个金属水平，同时始终确保将物理介电层支撑件提供给互连下面的器件结构。

公开(公告)号：US06858487B2

公开(公告)日：2005-02-22

申请号：US10334902

申请日：2003-01-02

申请人： Ming-Sheng Yang ,  Water Lur

发明人： Ming-Sheng Yang ,  Water Lur

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L29/6656

摘要： The present invention disclosed a method for manufacturing a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a gate dielectric layer on the semiconductor substrate. A gate is formed on the gate dielectric layer. A first ion implantation is performed to form extended source and drain shallow junctions in the semiconductor substrate. Spacer are formed on the side wall of the gate with liner between the gate and the spacers. The source and drain region is formed by performing a second ion implantation. A thermal annealing is used to eliminate the implantation defect and active the dopants. A surface treatment is used to form selective polycrystalline silicon on the gate and the source and drain region, thereby forming raised source and drain. A Cobalt layer is formed on the selective polycrystalline silicon. The Cobalt layer is reacted with the selective polycrystalline silicon on the gate and the raised source and drain region to form Cobalt silicide to eliminate the surface defect and lower sheet resistance of the source/drain regions.

摘要翻译： 本发明公开了一种在半导体衬底上制造半导体器件的方法，该方法包括以下步骤：在半导体衬底上形成栅介质层。 栅极形成在栅极电介质层上。 执行第一离子注入以在半导体衬底中形成扩展的源极和漏极浅结。 在栅极的侧壁上形成隔板，衬垫在栅极和间隔物之间​​。 通过执行第二离子注入形成源区和漏区。 使用热退火来消除注入缺陷并使掺杂剂活跃。 使用表面处理在栅极和源极和漏极区域上形成选择性多晶硅，由此形成升高的源极和漏极。 在选择性多晶硅上形成钴层。 钴层与栅极和升高的源极和漏极区上的选择性多晶硅反应以形成硅化钴，以消除源/漏区的表面缺陷和较低的薄层电阻。

公开(公告)号：US20050032328A1

公开(公告)日：2005-02-10

申请号：US10939716

申请日：2004-09-13

申请人： Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

发明人： Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21/762 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76229

摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

摘要翻译： 公开了用于形成浅沟槽隔离的化学机械抛光的方法。 提供了具有多个有效区域的基板，包括多个相对较大的有源区域和多个相对小的有源区域。 该方法包括以下步骤。 形成衬底上的氮化硅层。 在有源区域之间形成多个浅沟槽，其中一个或多个可以构成对准标记。 在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。 在氧化物层上形成部分反向有源掩模。 部分反向有源掩模将氧化物层的一部分暴露在大的有效区域上方和对准标记之上。 去除每个大活性区域的氧化物层和对准标记。 去除部分反向主动掩模。 氧化层平坦化。

公开(公告)号：US06677231B1

公开(公告)日：2004-01-13

申请号：US09715657

申请日：2000-11-17

申请人： Cheng-Yuan Tsai ,  Chin-Hsiang Lin ,  Ming-Sheng Yang

发明人： Cheng-Yuan Tsai ,  Chin-Hsiang Lin ,  Ming-Sheng Yang

IPC分类号： H01L214763

CPC分类号： H01L21/02304 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/3122 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832

摘要： A first dielectric layer 310 is formed on a substrate, wherein the first dielectric layer is a low-K material of an organic polymer. An adhesion promoter is then deposited on the first dielectric layer by chemical vapor deposition to form a first interlayer, wherein the first adhesion promoter is an organic material that comprises a C—H group and a siloxane (Si—O), such as methyltriacetoxysilane (MTAS). Next, an inorganic layer is formed on the first interlayer. Then the adhesion promoter mentioned previously is deposited on the inorganic layer by chemical vapor deposition to form a second interlayer. Next, a second dielectric layer is formed on the second interlayer 340, wherein the second interlayer is a low-K material of an organic polymer. Finally, a baking process is performed.

摘要翻译： 第一电介质层310形成在基底上，其中第一介电层是有机聚合物的低K材料。 然后通过化学气相沉积将粘附促进剂沉积在第一介电层上以形成第一中间层，其中第一粘合促进剂是包含CH基团和硅氧烷（Si-O）如甲基三乙酰氧基硅烷（MTAS）的有机材料， 。 接下来，在第一中间层上形成无机层。 然后通过化学气相沉积将上述粘附促进剂沉积在无机层上，形成第二层。 接下来，在第二中间层340上形成第二介电层，其中第二夹层是有机聚合物的低K材料。 最后，进行烘烤处理。

公开(公告)号：US06461230B1

公开(公告)日：2002-10-08

申请号：US09689045

申请日：2000-10-12

申请人： Teng-Chun Tsai ,  Hsueh-Chung Chen ,  Ming-Sheng Yang

发明人： Teng-Chun Tsai ,  Hsueh-Chung Chen ,  Ming-Sheng Yang

IPC分类号： B24B100

CPC分类号： B24B37/04 ,  B24B57/02 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/76807

摘要： A method for changing the polishing selectivity ratio of slurry used in chemical-mechanical polishing. Barrier slurry and a diluent are mixed together at different ratios to produce a mixture containing different amounts of solvent, chemicals and polishing particles. Hence, a variety of polishing selectivity ratios between copper film or barrier layer and other materials is obtained. The mixture is transported to the polishing pad of a polishing station to carry out chemical-mechanical polishing.

摘要翻译： 改变化学机械抛光中使用的浆料的抛光选择率的方法。 阻挡浆料和稀释剂以不同的比例混合在一起以产生含有不同量溶剂，化学品和抛光颗粒的混合物。 因此，可以获得铜膜或阻挡层与其它材料之间的各种抛光选择率。 将混合物输送到抛光站的抛光垫以进行化学机械抛光。

公开(公告)号：US06455432B1

公开(公告)日：2002-09-24

申请号：US09729220

申请日：2000-12-05

申请人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei ,  Ming-Sheng Yang

发明人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei ,  Ming-Sheng Yang

IPC分类号： H01L21461

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/31053 ,  Y10S438/906

摘要： A method for removing carbon-rich particles adhered on a copper surface, especially on a copper surface of a copper/low k dielectric dual damascene structure is provided. A barrier layer and a barrier-CMP stopping layer are formed between the copper layer and the low k dielectric layer of the dual damascene structure. After a Cu-CMP process and a barrier CMP process, a chemical buffing polishing process using an acidic aqueous solution under a downward force of about 0.5 to 3 psi is performed to remove carbon-rich particles adhered on the exposed copper surface, which is due to the low k dielectric layer having at least 90% carbon element being exposed and then polished during the Cu-CMP process and the barrier CMP process, resulting from a dishing phenomenon of the copper layer occurring during the two CMP processes. Alternately, a first chemical buffing polishing process is followed after the Cu-CMP process, and a second chemical buffing polishing process is followed after the barrier CMP process.

摘要翻译： 提供了一种去除附着在铜表面上的富碳颗粒的方法，特别是在铜/低k电介质双镶嵌结构的铜表面上。 在双镶嵌结构的铜层和低k电介质层之间形成阻挡层和阻挡CMP阻挡层。 在Cu-CMP工艺和阻挡CMP工艺之后，进行在约0.5至3psi的向下的力下使用酸性水溶液的化学抛光抛光工艺，以除去粘附在暴露的铜表面上的富碳颗粒，这是由于 到具有至少90％的碳元素的低k电介质层被暴露，然后在Cu-CMP工艺和阻挡CMP工艺期间被抛光，这是由于在两个CMP工艺期间发生的铜层的凹陷现象引起的。 或者，在Cu-CMP工艺之后进行第一次化学抛光抛光工艺，并且在阻挡CMP工艺之后遵循第二次化学抛光抛光工艺。

公开(公告)号：US06429115B1

公开(公告)日：2002-08-06

申请号：US09801330

申请日：2001-03-07

申请人： Cheng-Yuan Tsai ,  Chin-Hsiang Lin ,  Ming-Sheng Yang

发明人： Cheng-Yuan Tsai ,  Chin-Hsiang Lin ,  Ming-Sheng Yang

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

摘要： A method of manufacturing multilevel interconnects. A single or dual damascene interconnect structure is formed in a first dielectric layer. A cap layer or middle etch stop layer is formed over the interconnect structure and the first dielectric layer. The cap layer or the middle etch stop layer is treated with nitrogen plasma to convert a hydrophobic surface into a hydrophilic surface. An adhesion promoter layer is formed over the cap layer or middle etch stop layer. A low-k dielectric layer is formed over the adhesion promoter layer. A single or dual damascene structure is formed in the low-k dielectric layer, thereby forming a multilevel interconnect.

摘要翻译： 一种制造多层互连的方法。 单个或双镶嵌互连结构形成在第一介电层中。 在互连结构和第一介电层上形成覆盖层或中间蚀刻停止层。 用氮等离子体处理覆盖层或中间蚀刻停止层，以将疏水表面转化为亲水表面。 在覆盖层或中间蚀刻停止层上形成粘合促进剂层。 在粘合促进剂层上形成低k电介质层。 在低k电介质层中形成单个或双重镶嵌结构，从而形成多层互连。

公开(公告)号：US06403469B1

公开(公告)日：2002-06-11

申请号：US09660071

申请日：2000-09-12

申请人： Teng-Chun Tsai ,  Hsueh-Chung Chen ,  Ming-Sheng Yang

发明人： Teng-Chun Tsai ,  Hsueh-Chung Chen ,  Ming-Sheng Yang

IPC分类号： H01L214763

CPC分类号： H01L21/7684

摘要： A method of producing a dual damascene structure. A substrate is provided and an insulation layer is formed over the substrate. A dual damascene opening is formed in the insulation layer. A liner layer is formed over the exposed surface of the dual damascene opening. Metallic material is deposited over the substrate filling the dual damascene opening to form a metallic layer. A cap layer is formed over the metallic layer. A chemical-mechanical polishing operation is carried out to polish the cap layer using a metal-reactive solution or a cap-layer-reactive solution. The polishing operation continues until the cap layer outside the dual damascene opening is completely removed and the metallic layer is exposed. A portion of the cap layer remains above the dual damascene opening. Using the retained cap layer as a protective layer for the metallic layer, the metallic layer outside the dual damascene opening is removed by polishing until the liner layer is exposed. Lastly, the liner layer is removed to form a slightly protruding metal line structure.

摘要翻译： 一种制造双镶嵌结构的方法。 提供衬底并且在衬底上形成绝缘层。 在绝缘层中形成双镶嵌开口。 在双镶嵌开口的暴露表面上形成衬里层。 金属材料沉积在填充双镶嵌开口的基底上以形成金属层。 在金属层上形成覆盖层。 进行化学机械抛光操作以使用金属反应性溶液或盖层反应性溶液来抛光盖层。 抛光操作继续，直到双镶嵌开口外的盖层被完全去除并且金属层被暴露。 盖层的一部分保留在双镶嵌开口的上方。 使用保留的盖层作为金属层的保护层，通过抛光除去双镶嵌开口外侧的金属层直到衬里层露出。 最后，去除衬里层以形成稍微突出的金属线结构。