公开(公告)号：US20130302952A1

公开(公告)日：2013-11-14

申请号：US13580963

申请日：2012-06-07

申请人： Jun Luo ,  Jian Deng ,  Chao Zhao ,  Junfeng Li ,  Dapeng Chen

发明人： Jun Luo ,  Jian Deng ,  Chao Zhao ,  Junfeng Li ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a gate stack structure on a substrate; forming source and drain regions as well as a gate spacer on both sides of the gate stack structure; depositing a first metal layer on the source and drain regions; performing a first annealing such that the first metal layer reacts with the source and drain regions, to epitaxially grow a first metal silicide; depositing a second metal layer on the first metal silicide; and performing a second annealing such that the second metal layer reacts with the first metal silicide as well as the source and drain regions, to form a second metal silicide. In accordance with the method for manufacturing a semiconductor device of the present invention, by means of epitaxially growing an ultra-thin metal silicide on the source and drain regions, the grain boundaries among silicide particles are minimized or eliminated, the metal diffusion speed and direction are limited, thus the lateral growth of the metal silicide is suppressed and the device performance is further increased.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：在衬底上形成栅叠层结构; 在栅极堆叠结构的两侧形成源极和漏极区域以及栅极间隔物; 在所述源区和漏区上沉积第一金属层; 进行第一退火，使得第一金属层与源区和漏区反应，以外延生长第一金属硅化物; 在第一金属硅化物上沉积第二金属层; 以及执行第二退火，使得所述第二金属层与所述第一金属硅化物以及所述源极和漏极区域反应，以形成第二金属硅化物。 根据本发明的半导体器件的制造方法，通过在源极和漏极区域外延生长超薄金属硅化物，硅化物粒子之间的晶界被最小化或消除，金属扩散速度和方向 受限，金属硅化物的横向生长受到抑制，器件性能进一步提高。

公开(公告)号：US20130273669A1

公开(公告)日：2013-10-17

申请号：US13698283

申请日：2012-06-12

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC分类号： H01L21/306

CPC分类号： H01L21/30625 ,  H01L21/31053 ,  H01L21/31056 ,  H01L22/26 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.

摘要翻译： 本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二介电隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。 根据本发明的化学机械平面化方法的均匀性的方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差 并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

公开(公告)号：US20130213434A1

公开(公告)日：2013-08-22

申请号：US13497768

申请日：2011-11-28

申请人： Guilei Wang ,  Junfeng Li ,  Chao Zhao

发明人： Guilei Wang ,  Junfeng Li ,  Chao Zhao

IPC分类号： H01L21/02

CPC分类号： H01L21/02 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4404 ,  C23C16/505 ,  C23C16/56 ,  H01L21/76837

摘要： A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

摘要翻译： 公开了一种用于消除接触孔工艺中的接触桥的方法，其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单，使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。 叠层自适应保护薄膜具有良好的粘合性，紧凑性和均匀性，以保护HDP CVD设备室的侧壁不被等离子体损坏，并避免产生缺陷颗粒，从而提高HDP CVD技术产量并消除 接触孔过程中的接触桥现象。

公开(公告)号：US08486805B2

公开(公告)日：2013-07-16

申请号：US13142757

申请日：2011-04-11

申请人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

发明人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

IPC分类号： H01L21/30

CPC分类号： H01L21/76898 ,  H01L21/76224 ,  H01L2924/0002

摘要： A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

摘要翻译： 提供了一种硅通孔及其形成方法。 该方法包括：提供半导体衬底，所述半导体衬底包括上表面和相对的下表面; 蚀刻半导体衬底的上表面以形成开口; 用导电材料填充开口以形成第一钉; 蚀刻半导体衬底的下表面以形成凹部，使得第一指甲暴露在凹部的底部; 用可蚀刻的导电材料填充凹部，并蚀刻可蚀刻的导电材料以形成第二钉，使得第二钉与第一钉垂直连接; 以及在所述第二钉和所述半导体衬底之间填充间隙以及所述第二钉和相邻的具有介电层的第二钉之间的间隙。 然后，本发明可以提高硅通孔的可靠性并避免空隙。

公开(公告)号：US08420492B2

公开(公告)日：2013-04-16

申请号：US13143591

申请日：2011-01-27

申请人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7845

摘要： The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.

摘要翻译： 本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。 本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。

公开(公告)号：US20130059435A1

公开(公告)日：2013-03-07

申请号：US13510730

申请日：2011-11-30

申请人： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

发明人： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/51

摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

摘要翻译： 本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。 根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。 它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

公开(公告)号：US20130020618A1

公开(公告)日：2013-01-24

申请号：US13379347

申请日：2011-08-12

申请人： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

IPC分类号： H01L29/78 ,  H01L21/50

CPC分类号： H01L23/522 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.

摘要翻译： 提供半导体器件，其形成方法和封装结构。 半导体器件包括：形成金属氧化物半导体场效应晶体管（MOSFET）的半导体衬底; 介电层，设置在所述半导体衬底上并覆盖所述MOSFET，其中在所述电介质层中形成多个互连结构; 以及嵌入在互连结构之间的电介质层中的至少一个散热路径，用于使液体或气体在散热路径中循环，其中散热路径的开口暴露在介电层的表面上。 本发明可以提高散热效率，防止芯片过热。

公开(公告)号：US20120267706A1

公开(公告)日：2012-10-25

申请号：US13379373

申请日：2011-04-22

申请人： Jun Luo ,  Chao Zhao

发明人： Jun Luo ,  Chao Zhao

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66606 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional isolation spacer; source/drain regions located in the substrate on opposite sides of the gate stack structure; epitaxially grown metal silicide located on the source/drain regions; characterized in that, the epitaxially grown metal silicide is in direct contact with a channel region controlled by the gate stack structure, thereby eliminating the high resistance region below the conventional isolation spacer. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.

摘要翻译： 本发明公开了一种新颖的MOSFET器件及其实现方法，该器件包括：衬底; 栅极堆叠结构，其任一侧消除了常规隔离间隔物; 源极/漏极区域位于栅极堆叠结构的相对侧上的衬底中; 位于源/漏区上的外延生长金属硅化物; 其特征在于，外延生长的金属硅化物与由栅极堆叠结构控制的沟道区域直接接触，从而消除了传统隔离间隔物下面的高电阻区域。 同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。 根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

公开(公告)号：US20120244784A1

公开(公告)日：2012-09-27

申请号：US13142714

申请日：2011-04-11

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC分类号： B24B53/017 ,  B24B1/00

CPC分类号： B24B37/015 ,  B24B37/20 ,  B24B53/017 ,  Y02P80/30

摘要： A chemical-mechanical polishing tool and a method for preheating the same are disclosed. The chemical-mechanical polishing tool includes: a polishing pad, a deionized water supply channel, a polishing slurry supply channel and a polishing pad conditioner; and the chemical-mechanical polishing tool further includes: a heating apparatus, adapted to heat DI water fed to the DI water supply channel; a temperature sensor, arranged close to the polishing pad to measure a temperature of the polishing pad; and a preheating control system, connected to the temperature sensor, and adapted to control the DI water supply channel to spray the heated DI water to the polishing pad, and when the temperature measured by the temperature sensor is equal to or higher than a predetermined temperature, to close the DI water supply channel, control the polishing slurry supply channel to spray polishing slurry to the polishing pad, and startup the polishing pad conditioner to dress the polishing pad. The invention can reduce the consumption of polishing consumables by the chemical-mechanical polishing tool during preheating, thereby reducing production cost.

摘要翻译： 公开了一种化学机械抛光工具及其预热方法。 化学机械抛光工具包括：抛光垫，去离子水供应通道，抛光浆料供应通道和抛光垫调节剂; 并且所述化学机械抛光工具还包括：加热设备，其适于加热供给到所述DI供水通道的去离子水; 温度传感器，布置在抛光垫附近以测量抛光垫的温度; 以及预热控制系统，其连接到所述温度传感器，并且适于控制所述DI供水通道将所述加热的去离子水喷射到所述抛光垫，并且当所述温度传感器测量的温度等于或高于预定温度 关闭DI供水通道，控制抛光浆料供应通道将抛光浆料抛光到抛光垫上，并启动抛光垫调节剂来修整抛光垫。 本发明可以通过化学机械抛光工具在预热期间减少抛光耗材的消耗，从而降低生产成本。

公开(公告)号：US20120223431A1

公开(公告)日：2012-09-06

申请号：US13142757

申请日：2011-04-11

申请人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

发明人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

IPC分类号： H01L23/48 ,  H01L21/762

CPC分类号： H01L21/76898 ,  H01L21/76224 ,  H01L2924/0002

摘要： A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

摘要翻译： 提供了一种硅通孔及其形成方法。 该方法包括：提供半导体衬底，所述半导体衬底包括上表面和相对的下表面; 蚀刻半导体衬底的上表面以形成开口; 用导电材料填充开口以形成第一钉; 蚀刻半导体衬底的下表面以形成凹部，使得第一指甲暴露在凹部的底部; 用可蚀刻的导电材料填充凹部，并蚀刻可蚀刻的导电材料以形成第二钉，使得第二钉与第一钉垂直连接; 以及在所述第二钉和所述半导体衬底之间填充间隙以及所述第二钉和相邻的具有介电层的第二钉之间的间隙。 然后，本发明可以提高硅通孔的可靠性并避免空隙。