公开(公告)号：US07122863B1

公开(公告)日：2006-10-17

申请号：US09850393

申请日：2001-05-07

申请人： Dong-Hyuk Ju ,  William G. En ,  Srinath Krishnan ,  Xilin Judy An

发明人： Dong-Hyuk Ju ,  William G. En ,  Srinath Krishnan ,  Xilin Judy An

IPC分类号： H01L27/01

CPC分类号： H01L29/78612 ,  H01L29/78696

摘要： A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of the buried insulation layer, the oxide trap region having a plurality of oxide traps to promote carrier recombination.

摘要翻译： 绝缘体上半导体（SOI）器件。 SOI器件包括SOI晶片，其包括有源层，衬底和设置在其间的掩埋绝缘层。 掩埋绝缘层包括沿着掩埋绝缘层的上表面设置的氧化物陷阱区，氧化物阱区具有多个氧化物陷阱以促进载流子复合。

公开(公告)号：US06841832B1

公开(公告)日：2005-01-11

申请号：US10021497

申请日：2001-12-19

申请人： William G. En ,  Mark W. Michael ,  Hai Hong Wang ,  Simon Siu-Sing Chan

发明人： William G. En ,  Mark W. Michael ,  Hai Hong Wang ,  Simon Siu-Sing Chan

IPC分类号： H01L21/66 ,  H01L21/8234 ,  H01L23/544 ,  H01L27/08 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L22/34 ,  H01L21/823437 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

公开(公告)号：US06723666B1

公开(公告)日：2004-04-20

申请号：US10379792

申请日：2003-03-06

申请人： William G. En ,  Philip A. Fisher

发明人： William G. En ,  Philip A. Fisher

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/31662 ,  H01L29/518

摘要： Gate oxide surface irregularities, such as surface roughness, are reduced by treatment with an oxygen-containing plasma. Embodiments include forming a gate oxide layer and then treating the formed gate oxide layer with an oxygen plasma to repair weak spots and fill in pin holes and surface irregularities, thereby reducing gate/gate oxide interface roughness.

摘要翻译： 通过用含氧等离子体处理来减少氧化物表面凹凸，例如表面粗糙度。 实施例包括形成栅极氧化层，然后用氧等离子体处理形成的栅氧化层以修复弱点并填充针孔和表面凹凸，由此减小栅极/栅极氧化物界面粗糙度。

公开(公告)号：US06713357B1

公开(公告)日：2004-03-30

申请号：US10023348

申请日：2001-12-20

申请人： Hai Hong Wang ,  Mark W. Michael ,  Wen-Jie Qi ,  William G. En ,  John G. Pellerin

发明人： Hai Hong Wang ,  Mark W. Michael ,  Wen-Jie Qi ,  William G. En ,  John G. Pellerin

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L21/76834 ,  H01L23/3171 ,  H01L29/4983 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.

摘要翻译： 本发明涉及制造具有减小的寄生电容的MOS晶体管的方法。 本发明基于通过使用具有优化的横截面形状的侧壁间隔件与上覆绝缘体（例如CMOS）和IC器件的制造中的MOS晶体管的寄生电容相结合的方式， 层由低k电介质材料组成。

公开(公告)号：US06534381B2

公开(公告)日：2003-03-18

申请号：US09476916

申请日：2000-01-04

申请人： Nathan W. Cheung ,  William G. En ,  Sharon N. Farrens ,  Mikhail Korolik

发明人： Nathan W. Cheung ,  William G. En ,  Sharon N. Farrens ,  Mikhail Korolik

IPC分类号： H01L2130

CPC分类号： H01L21/76251

摘要： A method for forming a multi-layered substrate. The method includes forming a compliant layer on a face of a first substrate (10). Joining the compliant layer against a face of a second substrate (20), where the compliant layer forms around a surface non-uniformity on the second substrate face.

摘要翻译： 一种形成多层基板的方法。 该方法包括在第一衬底（10）的表面上形成柔顺层。 将柔性层接合在第二衬底（20）的表面上，其中柔顺层围绕第二衬底面上的表面不均匀地形成。

公开(公告)号：US06458723B1

公开(公告)日：2002-10-01

申请号：US09594464

申请日：2000-06-14

申请人： Francois J. Henley ,  Michael A. Bryan ,  William G. En

发明人： Francois J. Henley ,  Michael A. Bryan ,  William G. En

IPC分类号： H01L2126

CPC分类号： H01L21/67103 ,  H01J2237/2001 ,  H01J2237/31701

摘要： An ion implantation apparatus and method. The apparatus has a vacuum chamber and an ion beam generator to generate an ion beam in the vacuum chamber. The apparatus also has an implant wheel (10), in the vacuum chamber, having a plurality of circumferentially distributed substrate holding positions. Each of the substrate holding positions comprises a substrate holder (17), which includes an elastomer overlying the substrate holder (17) and a thermal insulating material (71) (e.g., quartz, silicon, ceramics, and other substantially non-compliant materials) overlying the elastomer (72). The present thermal insulating material increases a temperature of a substrate as it is implanted.

摘要翻译： 一种离子注入装置及方法。 该装置具有真空室和离子束发生器，以在真空室中产生离子束。 该设备还具有植入轮（10），其在真空室中具有多个周向分布的衬底保持位置。 每个基板保持位置包括基板保持器（17），其包括覆盖基板保持器（17）的弹性体和绝热材料（例如石英，硅，陶瓷和其他基本上不顺从的材料） 覆盖弹性体（72）。 本发明的绝热材料在植入时增加了基板的温度。

公开(公告)号：US06441433B1

公开(公告)日：2002-08-27

申请号：US09824412

申请日：2001-04-02

申请人： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

发明人： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC分类号： H01L3113

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.

摘要翻译： 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，器件包括形成在主源极和漏极区域以及源极和漏极延伸区域上的多层硅化物层，其中形成在源极和漏极延伸区域上的多层硅化物层的一部分比部分 形成在主源极和漏极区上的硅化物层。 该器件还包括形成在栅极的多晶硅电极上的第二薄硅化物层。