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    Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance
    1.
    发明授权
    Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance 失效
    用于测量栅介质厚度和寄生电容的栅介质结构阵列

    公开(公告)号：US06964875B1

    公开(公告)日：2005-11-15

    申请号：US10962582

    申请日：2004-10-13

    申请人： William G. En ,  Mark W. Michael ,  Hai Hong Wang ,  Simon Siu-Sing Chan

    发明人： William G. En ,  Mark W. Michael ,  Hai Hong Wang ,  Simon Siu-Sing Chan

    IPC分类号： H01L21/66 ,  H01L21/8234 ,  H01L23/544 ,  H01L27/08 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L22/34 ,  H01L21/823437 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

    摘要翻译： 制造高可靠性和高性能超薄栅极电介质半导体器件需要精确确定栅极电介质厚度。 具有超薄栅极介电层的大面积栅极介质电容器具有高栅极泄漏，这阻止了栅极电介质厚度的精确测量。 较小面积的电介质电容器的栅极电介质厚度的精确测量受到较小面积电容器的相对大的寄生电容的阻碍。 在晶片上形成第一和第二虚拟结构允许准确地确定栅极电介质厚度。 形成基本上类似于栅极介电电容器的第一和第二虚拟结构，除了第一虚拟结构形成而没有电容器的第二电极，并且第二虚拟结构形成而没有电容器结构的第一电极。 通过减去在第一和第二虚拟结构处测量的寄生电容来确定栅极介电电容器的电容，并因此确定厚度。

    Contact liner in integrated circuit technology
    8.
    发明授权
    Contact liner in integrated circuit technology 有权
    接触式衬板集成电路技术

    公开(公告)号：US07670915B1

    公开(公告)日：2010-03-02

    申请号：US10791096

    申请日：2004-03-01

    申请人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

    发明人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

    IPC分类号： H01L21/20

    CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成硅化物。 在半导体衬底的上方形成有具有接触孔的层间电介质。 接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。 接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。

    Reduction of lateral silicide growth in integrated circuit technology
    10.
    发明授权
    Reduction of lateral silicide growth in integrated circuit technology 有权
    降低集成电路技术中的侧硅化物生长

    公开(公告)号：US07064067B1

    公开(公告)日：2006-06-20

    申请号：US10770905

    申请日：2004-02-02

    申请人： Paul L. King ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Minh Van Ngo

    发明人： Paul L. King ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Minh Van Ngo

    IPC分类号： H01L21/336 ,  H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物。 在半导体衬底中形成源极/漏极结。 在源极/漏极区域和栅极上形成中间相硅化物。 去除侧壁间隔物。 由中间相硅化物形成最终相硅化物。 在半导体衬底上沉积层间电介质，然后在层间电介质中形成接触到最终相硅化物。